5 #include <ppc_asm.tmpl>
11 #ifndef CACHE_LINE_SIZE
12 # define CACHE_LINE_SIZE L1_CACHE_BYTES
15 #if CACHE_LINE_SIZE == 128
16 #define LG_CACHE_LINE_SIZE 7
17 #elif CACHE_LINE_SIZE == 32
18 #define LG_CACHE_LINE_SIZE 5
19 #elif CACHE_LINE_SIZE == 16
20 #define LG_CACHE_LINE_SIZE 4
21 #elif CACHE_LINE_SIZE == 8
22 #define LG_CACHE_LINE_SIZE 3
24 # error "Invalid cache line size!"
28 * Invalidate L1 instruction cache.
30 _GLOBAL(invalidate_l1_instruction_cache)
34 beqlr /* for 601, do nothing */
35 /* 603/604 processor - use invalidate-all bit in HID0 */
43 * Invalidate L1 data cache.
45 _GLOBAL(invalidate_l1_data_cache)
55 _GLOBAL(flush_data_cache)
57 lis r5,CACHE_LINE_SIZE
62 lis r5,CACHE_LINE_SIZE
68 * Write any modified data cache blocks out to memory
69 * and invalidate the corresponding instruction cache blocks.
70 * This is a no-op on the 601.
72 * flush_icache_range(unsigned long start, unsigned long stop)
74 _GLOBAL(flush_icache_range)
78 beqlr /* for 601, do nothing */
79 li r5,CACHE_LINE_SIZE-1
83 srwi. r4,r4,LG_CACHE_LINE_SIZE
88 addi r3,r3,CACHE_LINE_SIZE
90 sync /* wait for dcbst's to get to ram */
93 addi r6,r6,CACHE_LINE_SIZE
95 sync /* additional sync needed on g4 */
99 * Write any modified data cache blocks out to memory.
100 * Does not invalidate the corresponding cache lines (especially for
101 * any corresponding instruction cache).
103 * clean_dcache_range(unsigned long start, unsigned long stop)
105 _GLOBAL(clean_dcache_range)
106 li r5,CACHE_LINE_SIZE-1
107 andc r3,r3,r5 /* align r3 down to cache line */
108 subf r4,r3,r4 /* r4 = offset of stop from start of cache line */
109 add r4,r4,r5 /* r4 += cache_line_size-1 */
110 srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */
111 beqlr /* if r4 == 0 return */
112 mtctr r4 /* ctr = r4 */
116 addi r3,r3,CACHE_LINE_SIZE
118 sync /* wait for dcbst's to get to ram */
122 * Write any modified data cache blocks out to memory
123 * and invalidate the corresponding instruction cache blocks.
125 * flush_dcache_range(unsigned long start, unsigned long stop)
127 _GLOBAL(flush_dcache_range)
128 li r5,CACHE_LINE_SIZE-1
132 srwi. r4,r4,LG_CACHE_LINE_SIZE
138 addi r3,r3,CACHE_LINE_SIZE
140 sync /* wait for dcbf's to get to ram */
144 * Like above, but invalidate the D-cache. This is used by the 8xx
145 * to invalidate the cache so the PPC core doesn't get stale data
146 * from the CPM (no cache snooping here :-).
148 * invalidate_dcache_range(unsigned long start, unsigned long stop)
150 _GLOBAL(invalidate_dcache_range)
151 li r5,CACHE_LINE_SIZE-1
155 srwi. r4,r4,LG_CACHE_LINE_SIZE
161 addi r3,r3,CACHE_LINE_SIZE
163 sync /* wait for dcbi's to get to ram */
167 * Flush a particular page from the data cache to RAM.
168 * Note: this is necessary because the instruction cache does *not*
169 * snoop from the data cache.
170 * This is a no-op on the 601 which has a unified cache.
172 * void __flush_page_to_ram(void *page)
174 _GLOBAL(__flush_page_to_ram)
176 rlwinm r5,r5,16,16,31
178 beqlr /* for 601, do nothing */
179 rlwinm r3,r3,0,0,19 /* Get page base address */
180 li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
183 0: dcbst 0,r3 /* Write line to ram */
184 addi r3,r3,CACHE_LINE_SIZE
189 addi r6,r6,CACHE_LINE_SIZE
196 * Flush a particular page from the instruction cache.
197 * Note: this is necessary because the instruction cache does *not*
198 * snoop from the data cache.
199 * This is a no-op on the 601 which has a unified cache.
201 * void __flush_icache_page(void *page)
203 _GLOBAL(__flush_icache_page)
205 rlwinm r5,r5,16,16,31
207 beqlr /* for 601, do nothing */
208 li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
211 addi r3,r3,CACHE_LINE_SIZE
218 * Clear a page using the dcbz instruction, which doesn't cause any
219 * memory traffic (except to write out any cache lines which get
220 * displaced). This only works on cacheable memory.
223 li r0,4096/CACHE_LINE_SIZE
226 addi r3,r3,CACHE_LINE_SIZE
231 * Enable L1 Instruction cache
233 _GLOBAL(icache_enable)
235 li r5, HID0_ICFI|HID0_ILOCK
238 ori r5, r3, HID0_ICFI
245 * Disable L1 Instruction cache
247 _GLOBAL(icache_disable)
257 * Is instruction cache enabled?
259 _GLOBAL(icache_status)
261 andi. r3, r3, HID0_ICE
265 _GLOBAL(l1dcache_enable)
267 li r5, HID0_DCFI|HID0_DLOCK
269 mtspr HID0, r3 /* no invalidate, unlock */
271 ori r5, r3, HID0_DCFI
272 mtspr HID0, r5 /* enable + invalidate */
273 mtspr HID0, r3 /* enable */
278 * Enable data cache(s) - L1 and optionally L2
279 * Calls l2cache_enable. LR saved in r5
281 _GLOBAL(dcache_enable)
283 li r5, HID0_DCFI|HID0_DLOCK
285 mtspr HID0, r3 /* no invalidate, unlock */
287 ori r5, r3, HID0_DCFI
288 mtspr HID0, r5 /* enable + invalidate */
289 mtspr HID0, r3 /* enable */
293 bl l2cache_enable /* uses r3 and r4 */
301 * Disable data cache(s) - L1 and optionally L2
302 * Calls flush_data_cache and l2cache_disable_no_flush.
305 _GLOBAL(dcache_disable)
306 mflr r4 /* save link register */
307 bl flush_data_cache /* uses r3 and r5 */
310 li r5, HID0_DCFI|HID0_DLOCK
312 mtspr HID0, r3 /* no invalidate, unlock */
313 li r5, HID0_DCE|HID0_DCFI
314 andc r3, r3, r5 /* no enable, no invalidate */
318 bl l2cache_disable_no_flush /* uses r3 */
320 mtlr r4 /* restore link register */
324 * Is data cache enabled?
326 _GLOBAL(dcache_status)
328 andi. r3, r3, HID0_DCE
332 * Invalidate L2 cache using L2I and polling L2IP or L2I
334 _GLOBAL(l2cache_invalidate)
337 oris r3, r3, L2CR_L2I@h
343 rlwinm r3, r3, 16,16,31
344 cmpli 0,r3,0x8000 /* 7451, 7441 */
346 cmpli 0,r3,0x8001 /* 7455, 7445 */
348 cmpli 0,r3,0x8002 /* 7457, 7447 */
350 cmpli 0,r3,0x8003 /* 7447A */
352 cmpli 0,r3,0x8004 /* 7448 */
356 andi. r3, r3, L2CR_L2IP
358 /* turn off the global invalidate bit */
360 rlwinm r3, r3, 0, 11, 9
367 andis. r3, r3, L2CR_L2I@h
373 * Calls l2cache_invalidate. LR is saved in r4
375 _GLOBAL(l2cache_enable)
376 mflr r4 /* save link register */
377 bl l2cache_invalidate /* uses r3 */
380 ori r3, r3, L2_ENABLE@l
383 mtlr r4 /* restore link register */
388 * Calls flush_data_cache. LR is saved in r4
390 _GLOBAL(l2cache_disable)
391 mflr r4 /* save link register */
392 bl flush_data_cache /* uses r3 and r5 */
394 mtlr r4 /* restore link register */
395 l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */
397 ori r3, r3, L2_INIT@l