3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * written or collected and sometimes rewritten by
30 * Magnus Damm <damm@bitsmart.com>
32 * minor modifications by
33 * Wolfgang Denk <wd@denx.de>
35 * more modifications by
36 * Josh Huber <huber@mclx.com>
37 * added support for the 74xx series of cpus
38 * added support for the 7xx series of cpus
39 * made the code a little less hard-coded, and more auto-detectish
45 #include <asm/cache.h>
47 #if defined(CONFIG_OF_LIBFDT)
49 #include <fdt_support.h>
52 #if defined(CONFIG_OF_FLAT_TREE)
56 #ifdef CONFIG_AMIGAONEG3SE
57 #include "../board/MAI/AmigaOneG3SE/via686.h"
58 #include "../board/MAI/AmigaOneG3SE/memio.h"
61 DECLARE_GLOBAL_DATA_PTR;
71 switch (PVR_VER(pvr)) {
78 if (((pvr >> 8) & 0xff) == 0x01) {
79 type = CPU_750CX; /* old CX (80100 and 8010x?)*/
80 } else if (((pvr >> 8) & 0xff) == 0x22) {
81 type = CPU_750CX; /* CX (82201,82202) and CXe (82214) */
82 } else if (((pvr >> 8) & 0xff) == 0x33) {
83 type = CPU_750CX; /* CXe (83311) */
84 } else if (((pvr >> 12) & 0xF) == 0x3) {
128 /* ------------------------------------------------------------------------- */
130 #if !defined(CONFIG_BAB7xx)
133 uint type = get_cpu_type();
134 uint pvr = get_pvr();
135 ulong clock = gd->cpu_clk;
143 printf ("750CX%s v%d.%d", (pvr&0xf0)?"e":"",
193 printf("Unknown CPU -- PVR: 0x%08x\n", pvr);
197 printf ("%s v%d.%d", str, (pvr >> 8) & 0xFF, pvr & 0xFF);
199 printf (" @ %s MHz\n", strmhz(buf, clock));
204 /* these two functions are unimplemented currently [josh] */
206 /* -------------------------------------------------------------------- */
215 /* -------------------------------------------------------------------- */
224 /* -------------------------------------------------------------------- */
227 soft_restart(unsigned long addr)
229 /* SRR0 has system reset vector, SRR1 has default MSR value */
230 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
232 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
233 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
234 __asm__ __volatile__ ("mtspr 27, 4");
235 __asm__ __volatile__ ("rfi");
237 while(1); /* not reached */
241 #if !defined(CONFIG_PCIPPC2) && \
242 !defined(CONFIG_BAB7xx) && \
243 !defined(CONFIG_ELPPC) && \
244 !defined(CONFIG_PPMC7XX)
245 /* no generic way to do board reset. simply call soft_reset. */
247 do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
250 /* flush and disable I/D cache */
251 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
252 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
253 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
254 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
255 __asm__ __volatile__ ("sync");
256 __asm__ __volatile__ ("mtspr 1008, 4");
257 __asm__ __volatile__ ("isync");
258 __asm__ __volatile__ ("sync");
259 __asm__ __volatile__ ("mtspr 1008, 5");
260 __asm__ __volatile__ ("isync");
261 __asm__ __volatile__ ("sync");
263 #ifdef CFG_RESET_ADDRESS
264 addr = CFG_RESET_ADDRESS;
267 * note: when CFG_MONITOR_BASE points to a RAM address,
268 * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
269 * address. Better pick an address known to be invalid on your
270 * system and assign it to CFG_RESET_ADDRESS.
272 addr = CFG_MONITOR_BASE - sizeof (ulong);
275 while(1); /* not reached */
279 /* ------------------------------------------------------------------------- */
282 * For the 7400 the TB clock runs at 1/4 the cpu bus speed.
284 #if defined(CONFIG_AMIGAONEG3SE) || defined(CFG_CONFIG_BUS_CLK)
285 unsigned long get_tbclk(void)
287 return (gd->bus_clk / 4);
289 #else /* ! CONFIG_AMIGAONEG3SE and !CFG_CONFIG_BUS_CLK*/
291 unsigned long get_tbclk (void)
293 return CFG_BUS_HZ / 4;
295 #endif /* CONFIG_AMIGAONEG3SE or CFG_CONFIG_BUS_CLK*/
296 /* ------------------------------------------------------------------------- */
297 #if defined(CONFIG_WATCHDOG)
298 #if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx)
304 #endif /* !CONFIG_PCIPPC2 && !CONFIG_BAB7xx */
305 #endif /* CONFIG_WATCHDOG */
307 /* ------------------------------------------------------------------------- */
309 #ifdef CONFIG_OF_LIBFDT
310 void ft_cpu_setup(void *blob, bd_t *bd)
312 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
313 "timebase-frequency", bd->bi_busfreq / 4, 1);
314 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
315 "bus-frequency", bd->bi_busfreq, 1);
316 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
317 "clock-frequency", bd->bi_intfreq, 1);
319 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
321 fdt_fixup_ethernet(blob, bd);
324 /* ------------------------------------------------------------------------- */