3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/proc-armv/ptrace.h>
32 #include <asm/hardware.h>
35 /* we always count down the max. */
36 #define TIMER_LOAD_VAL 0xffff
37 /* macro to read the 16 bit timer */
38 #define READ_TIMER (IO_TC1D & 0xffff)
42 #define READ_TIMER (0xFFFFFFFF - GET32(T0TC))
46 #define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
47 #define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
48 #define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
49 #define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
50 #define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
53 #ifdef CONFIG_S3C4510B
54 /* require interrupts for the S3C4510B */
55 # ifndef CONFIG_USE_IRQ
56 # error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
58 static struct _irq_handler IRQ_HANDLER[N_IRQS];
60 #endif /* CONFIG_S3C4510B */
63 /* enable IRQ/FIQ interrupts */
64 void enable_interrupts (void)
67 __asm__ __volatile__("mrs %0, cpsr\n"
77 * disable IRQ/FIQ interrupts
78 * returns true if interrupts had been enabled before we disabled them
80 int disable_interrupts (void)
82 unsigned long old,temp;
83 __asm__ __volatile__("mrs %0, cpsr\n"
86 : "=r" (old), "=r" (temp)
89 return (old & 0x80) == 0;
91 #else /* CONFIG_USE_IRQ */
92 void enable_interrupts (void)
96 int disable_interrupts (void)
104 panic ("Resetting CPU ...\n");
108 void show_regs (struct pt_regs *regs)
111 const char *processor_modes[] =
112 { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26",
114 "UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26",
115 "UK14_26", "UK15_26",
116 "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32",
118 "UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32",
122 flags = condition_codes (regs);
124 printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
125 "sp : %08lx ip : %08lx fp : %08lx\n",
126 instruction_pointer (regs),
127 regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
128 printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
129 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
130 printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
131 regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
132 printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
133 regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
134 printf ("Flags: %c%c%c%c",
135 flags & CC_N_BIT ? 'N' : 'n',
136 flags & CC_Z_BIT ? 'Z' : 'z',
137 flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
138 printf (" IRQs %s FIQs %s Mode %s%s\n",
139 interrupts_enabled (regs) ? "on" : "off",
140 fast_interrupts_enabled (regs) ? "on" : "off",
141 processor_modes[processor_mode (regs)],
142 thumb_mode (regs) ? " (T)" : "");
145 void do_undefined_instruction (struct pt_regs *pt_regs)
147 printf ("undefined instruction\n");
152 void do_software_interrupt (struct pt_regs *pt_regs)
154 printf ("software interrupt\n");
159 void do_prefetch_abort (struct pt_regs *pt_regs)
161 printf ("prefetch abort\n");
166 void do_data_abort (struct pt_regs *pt_regs)
168 printf ("data abort\n");
173 void do_not_used (struct pt_regs *pt_regs)
175 printf ("not used\n");
180 void do_fiq (struct pt_regs *pt_regs)
182 printf ("fast interrupt request\n");
187 void do_irq (struct pt_regs *pt_regs)
189 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO)
190 printf ("interrupt request\n");
193 #elif defined(CONFIG_S3C4510B)
194 unsigned int pending;
196 while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */
197 IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
199 /* clear pending interrupt */
200 PUT_REG( REG_INTPEND, (1<<(pending>>2)));
202 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
203 /* No do_irq() for IntegratorAP/CM720T as yet */
204 #elif defined(CONFIG_LPC2292)
208 pfnct = (void (*)(void))VICVectAddr;
212 #error do_irq() not defined for this CPU type
217 #ifdef CONFIG_S3C4510B
218 static void default_isr( void *data) {
219 printf ("default_isr(): called for IRQ %d\n", (int)data);
222 static void timer_isr( void *data) {
223 unsigned int *pTime = (unsigned int *)data;
226 if ( !(*pTime % (CFG_HZ/4))) {
228 PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
234 #if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
235 /* Use IntegratorAP routines in board/integratorap.c */
238 static ulong timestamp;
239 static ulong lastdec;
241 int interrupt_init (void)
244 #if defined(CONFIG_NETARM)
245 /* disable all interrupts */
248 /* operate timer 2 in non-prescale mode */
249 TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CFG_HZ) |
250 NETARM_GEN_TCTL_ENABLE |
251 NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
253 /* set timer 2 counter */
254 lastdec = TIMER_LOAD_VAL;
255 #elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
256 /* disable all interrupts */
259 /* operate timer 1 in prescale mode */
260 IO_SYSCON1 |= SYSCON1_TC1M;
262 /* select 2kHz clock source for timer 1 */
263 IO_SYSCON1 &= ~SYSCON1_TC1S;
265 /* set timer 1 counter */
266 lastdec = IO_TC1D = TIMER_LOAD_VAL;
267 #elif defined(CONFIG_S3C4510B)
270 /* install default interrupt handlers */
271 for ( i = 0; i < N_IRQS; i++) {
272 IRQ_HANDLER[i].m_data = (void *)i;
273 IRQ_HANDLER[i].m_func = default_isr;
276 /* configure interrupts for IRQ mode */
277 PUT_REG( REG_INTMODE, 0x0);
278 /* clear any pending interrupts */
279 PUT_REG( REG_INTPEND, 0x1FFFFF);
283 /* install interrupt handler for timer */
284 IRQ_HANDLER[INT_TIMER0].m_data = (void *)×tamp;
285 IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
287 /* configure free running timer 0 */
288 PUT_REG( REG_TMOD, 0x0);
290 CLR_REG( REG_TMOD, TM0_RUN);
292 /* Configure for interval mode */
293 CLR_REG( REG_TMOD, TM1_TOGGLE);
296 * Load Timer data register with count down value.
297 * count_down_val = CFG_SYS_CLK_FREQ/CFG_HZ
299 PUT_REG( REG_TDATA0, (CFG_SYS_CLK_FREQ / CFG_HZ));
302 * Enable global interrupt
303 * Enable timer0 interrupt
305 CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
308 SET_REG( REG_TMOD, TM0_RUN);
309 #elif defined(CONFIG_LPC2292)
310 PUT32(T0IR, 0); /* disable all timer0 interrupts */
311 PUT32(T0TCR, 0); /* disable timer0 */
312 PUT32(T0PR, CFG_SYS_CLK_FREQ / CFG_HZ);
315 PUT32(T0TCR, 1); /* enable timer0 */
318 #error No interrupt_init() defined for this CPU type
325 #endif /* ! IntegratorAP */
328 * timer without interrupts
332 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM) || defined(CONFIG_ARMADILLO) || defined(CONFIG_LPC2292)
334 void reset_timer (void)
336 reset_timer_masked ();
339 ulong get_timer (ulong base)
341 return get_timer_masked () - base;
344 void set_timer (ulong t)
349 void udelay (unsigned long usec)
357 tmo += get_timer (0);
359 while (get_timer_masked () < tmo)
360 #ifdef CONFIG_LPC2292
361 /* GJ - not sure whether this is really needed or a misunderstanding */
362 __asm__ __volatile__(" nop");
368 void reset_timer_masked (void)
371 lastdec = READ_TIMER;
375 ulong get_timer_masked (void)
377 ulong now = READ_TIMER;
379 if (lastdec >= now) {
381 timestamp += lastdec - now;
383 /* we have an overflow ... */
384 timestamp += lastdec + TIMER_LOAD_VAL - now;
391 void udelay_masked (unsigned long usec)
406 endtime = get_timer_masked () + tmo;
409 ulong now = get_timer_masked ();
410 diff = endtime - now;
414 #elif defined(CONFIG_S3C4510B)
416 ulong get_timer (ulong base)
418 return timestamp - base;
421 void udelay (unsigned long usec)
425 ticks = (usec * CFG_HZ) / 1000000;
427 ticks += get_timer (0);
429 while (get_timer (0) < ticks)
434 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
435 /* No timer routines for IntegratorAP/CM720T as yet */
437 #error Timer routines not defined for this CPU type