2 * armboot - Startup Code for ARM720 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/netarm_registers.h>
34 *************************************************************************
36 * Jump vector table as in table 3.1 in [1]
38 *************************************************************************
44 ldr pc, _undefined_instruction
45 ldr pc, _software_interrupt
46 ldr pc, _prefetch_abort
52 _undefined_instruction: .word undefined_instruction
53 _software_interrupt: .word software_interrupt
54 _prefetch_abort: .word prefetch_abort
55 _data_abort: .word data_abort
56 _not_used: .word not_used
60 .balignl 16,0xdeadbeef
64 *************************************************************************
66 * Startup Code (reset vector)
68 * do important init only if we don't start from RAM!
69 * relocate armboot to ram
71 * jump to second stage
73 *************************************************************************
84 * These are defined in the board-specific linker script.
95 /* IRQ stack memory (calculated at run-time) */
96 .globl IRQ_STACK_START
100 /* IRQ stack memory (calculated at run-time) */
101 .globl FIQ_STACK_START
108 * the actual reset code
113 * set the cpu to SVC32 mode
121 * we do sys-critical inits only at reboot,
122 * not when booting from ram!
124 #ifdef CONFIG_INIT_CRITICAL
128 relocate: /* relocate U-Boot to RAM */
129 adr r0, _start /* r0 <- current position of code */
130 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
131 cmp r0, r1 /* don't reloc during debug */
134 ldr r2, _armboot_start
136 sub r2, r3, r2 /* r2 <- size of armboot */
137 add r2, r0, r2 /* r2 <- source end address */
140 ldmia r0!, {r3-r10} /* copy from source address [r0] */
141 stmia r1!, {r3-r10} /* copy to target address [r1] */
142 cmp r0, r2 /* until source end addreee [r2] */
145 /* Set up the stack */
147 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
148 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
149 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
150 #ifdef CONFIG_USE_IRQ
151 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
153 sub sp, r0, #12 /* leave 3 words for abort-stack */
156 ldr r0, _bss_start /* find start of bss segment */
157 add r0, r0, #4 /* start at first byte of bss */
158 ldr r1, _bss_end /* stop here */
159 mov r2, #0x00000000 /* clear */
161 clbss_l:str r2, [r0] /* clear loop... */
166 ldr pc, _start_armboot
168 _start_armboot: .word start_armboot
172 *************************************************************************
174 * CPU_init_critical registers
176 * setup important registers
177 * setup memory timing
179 *************************************************************************
183 /* Interupt-Controller base addresses */
184 INTMR1: .word 0x80000280 @ 32 bit size
185 INTMR2: .word 0x80001280 @ 16 bit size
186 INTMR3: .word 0x80002280 @ 8 bit size
189 SYSCON1: .word 0x80000100
190 SYSCON2: .word 0x80001100
191 SYSCON3: .word 0x80002200
193 #define CLKCTL 0x6 /* mask */
194 #define CLKCTL_18 0x0 /* 18.432 MHz */
195 #define CLKCTL_36 0x2 /* 36.864 MHz */
196 #define CLKCTL_49 0x4 /* 49.152 MHz */
197 #define CLKCTL_73 0x6 /* 73.728 MHz */
200 #ifndef CONFIG_NETARM
202 * mask all IRQs by clearing all bits in the INTMRs
213 * flush v4 I/D caches
216 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
217 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
220 * disable MMU stuff and caches
223 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
224 bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
225 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
227 #else /* CONFIG_NETARM */
229 * prior to software reset : need to set pin PORTC4 to be *HRESET
231 ldr r0, =NETARM_GEN_MODULE_BASE
232 ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \
233 NETARM_GEN_PORT_DIR(0x10))
234 str r1, [r0, #+NETARM_GEN_PORTC]
236 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
237 * for an explanation of this process
239 ldr r0, =NETARM_GEN_MODULE_BASE
240 ldr r1, =NETARM_GEN_SW_SVC_RESETA
241 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
242 ldr r1, =NETARM_GEN_SW_SVC_RESETB
243 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
244 ldr r1, =NETARM_GEN_SW_SVC_RESETA
245 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
246 ldr r1, =NETARM_GEN_SW_SVC_RESETB
247 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
249 * setup PLL and System Config
251 ldr r0, =NETARM_GEN_MODULE_BASE
253 ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \
254 NETARM_GEN_SYS_CFG_BUSFULL | \
255 NETARM_GEN_SYS_CFG_USER_EN | \
256 NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
257 NETARM_GEN_SYS_CFG_BUSARB_INT | \
258 NETARM_GEN_SYS_CFG_BUSMON_EN )
260 str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
262 ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
263 NETARM_GEN_PLL_CTL_POLTST_DEF | \
264 NETARM_GEN_PLL_CTL_INDIV(1) | \
265 NETARM_GEN_PLL_CTL_ICP_DEF | \
266 NETARM_GEN_PLL_CTL_OUTDIV(2) )
267 str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
269 * mask all IRQs by clearing all bits in the INTMRs
272 ldr r0, =NETARM_GEN_MODULE_BASE
273 str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
274 #endif /* CONFIG_NETARM */
276 #ifdef CONFIG_ARM7_REVD
277 /* set clock speed */
278 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
279 /* !!! not doing DRAM refresh properly! */
283 orr r1, r1, #CLKCTL_36
288 * before relocating, we have to setup RAM timing
289 * because memory timing is board-dependent, you will
290 * find a memsetup.S in your board directory.
300 *************************************************************************
304 *************************************************************************
310 #define S_FRAME_SIZE 72
332 #define MODE_SVC 0x13
336 * use bad_save_user_regs for abort/prefetch/undef/swi ...
337 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
340 .macro bad_save_user_regs
341 sub sp, sp, #S_FRAME_SIZE
342 stmia sp, {r0 - r12} @ Calling r0-r12
345 ldr r2, _armboot_start
346 sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
347 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
348 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
349 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
353 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
357 .macro irq_save_user_regs
358 sub sp, sp, #S_FRAME_SIZE
359 stmia sp, {r0 - r12} @ Calling r0-r12
361 stmdb r8, {sp, lr}^ @ Calling SP, LR
362 str lr, [r8, #0] @ Save calling PC
364 str r6, [r8, #4] @ Save CPSR
365 str r0, [r8, #8] @ Save OLD_R0
369 .macro irq_restore_user_regs
370 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
372 ldr lr, [sp, #S_PC] @ Get PC
373 add sp, sp, #S_FRAME_SIZE
374 subs pc, lr, #4 @ return & move spsr_svc into cpsr
378 ldr r13, _armboot_start @ setup our mode stack
379 sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
380 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
382 str lr, [r13] @ save caller lr / spsr
386 mov r13, #MODE_SVC @ prepare SVC-Mode
392 .macro get_irq_stack @ setup IRQ stack
393 ldr sp, IRQ_STACK_START
396 .macro get_fiq_stack @ setup FIQ stack
397 ldr sp, FIQ_STACK_START
404 undefined_instruction:
407 bl do_undefined_instruction
413 bl do_software_interrupt
433 #ifdef CONFIG_USE_IRQ
440 irq_restore_user_regs
445 /* someone ought to write a more effiction fiq_save_user_regs */
448 irq_restore_user_regs
469 #ifndef CONFIG_NETARM
471 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
472 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
473 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
474 bic ip, ip, #0x000f @ ............wcam
475 bic ip, ip, #0x2100 @ ..v....s........
476 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
479 ldr r1, =NETARM_MEM_MODULE_BASE
480 ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
483 ldr r1, =(relocate-TEXT_BASE)
485 ldr r4, =NETARM_GEN_MODULE_BASE
486 ldr r1, =NETARM_GEN_SW_SVC_RESETA
487 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
488 ldr r1, =NETARM_GEN_SW_SVC_RESETB
489 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
490 ldr r1, =NETARM_GEN_SW_SVC_RESETA
491 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
492 ldr r1, =NETARM_GEN_SW_SVC_RESETB
493 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]