2 * armboot - Startup Code for ARM720 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
50 _undefined_instruction: .word undefined_instruction
51 _software_interrupt: .word software_interrupt
52 _prefetch_abort: .word prefetch_abort
53 _data_abort: .word data_abort
54 _not_used: .word not_used
58 .balignl 16,0xdeadbeef
62 *************************************************************************
64 * Startup Code (reset vector)
66 * do important init only if we don't start from memory!
67 * relocate armboot to ram
69 * jump to second stage
71 *************************************************************************
82 * Note: _armboot_end_data and _armboot_end are defined
83 * by the (board-dependent) linker script.
84 * _armboot_end_data is the first usable FLASH address after armboot
86 .globl _armboot_end_data
88 .word armboot_end_data
94 /* IRQ stack memory (calculated at run-time) */
95 .globl IRQ_STACK_START
99 /* IRQ stack memory (calculated at run-time) */
100 .globl FIQ_STACK_START
107 * the actual reset code
112 * set the cpu to SVC32 mode
120 * we do sys-critical inits only at reboot,
121 * not when booting from ram!
123 #ifdef CONFIG_INIT_CRITICAL
127 relocate: /* relocate U-Boot to RAM */
128 adr r0, _start /* r0 <- current position of code */
129 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
130 cmp r0, r1 /* don't reloc during debug */
133 ldr r2, _armboot_start
135 sub r2, r3, r2 /* r2 <- size of armboot */
136 add r2, r0, r2 /* r2 <- source end address */
139 ldmia r0!, {r3-r10} /* copy from source address [r0] */
140 stmia r1!, {r3-r10} /* copy to target address [r1] */
141 cmp r0, r2 /* until source end addreee [r2] */
144 /* Set up the stack */
146 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
147 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
148 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
149 #ifdef CONFIG_USE_IRQ
150 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
152 sub sp, r0, #12 /* leave 3 words for abort-stack */
154 ldr pc, _start_armboot
156 _start_armboot: .word start_armboot
160 *************************************************************************
162 * CPU_init_critical registers
164 * setup important registers
165 * setup memory timing
167 *************************************************************************
171 /* Interupt-Controller base addresses */
172 INTMR1: .word 0x80000280 @ 32 bit size
173 INTMR2: .word 0x80001280 @ 16 bit size
174 INTMR3: .word 0x80002280 @ 8 bit size
177 SYSCON1: .word 0x80000100
178 SYSCON2: .word 0x80001100
179 SYSCON3: .word 0x80002200
181 #define CLKCTL 0x6 /* mask */
182 #define CLKCTL_18 0x0 /* 18.432 MHz */
183 #define CLKCTL_36 0x2 /* 36.864 MHz */
184 #define CLKCTL_49 0x4 /* 49.152 MHz */
185 #define CLKCTL_73 0x6 /* 73.728 MHz */
189 * mask all IRQs by clearing all bits in the INTMRs
200 * flush v4 I/D caches
203 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
204 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
207 * disable MMU stuff and caches
210 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
211 bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
212 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
215 #ifdef CONFIG_ARM7_REVD
216 /* set clock speed */
217 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
218 /* !!! not doing DRAM refresh properly! */
222 orr r1, r1, #CLKCTL_36
227 * before relocating, we have to setup RAM timing
228 * because memory timing is board-dependend, you will
229 * find a memsetup.S in your board directory.
239 *************************************************************************
243 *************************************************************************
249 #define S_FRAME_SIZE 72
271 #define MODE_SVC 0x13
275 * use bad_save_user_regs for abort/prefetch/undef/swi ...
276 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
279 .macro bad_save_user_regs
280 sub sp, sp, #S_FRAME_SIZE
281 stmia sp, {r0 - r12} @ Calling r0-r12
285 add r2, r2, #CONFIG_STACKSIZE
287 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
288 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
292 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
296 .macro irq_save_user_regs
297 sub sp, sp, #S_FRAME_SIZE
298 stmia sp, {r0 - r12} @ Calling r0-r12
300 stmdb r8, {sp, lr}^ @ Calling SP, LR
301 str lr, [r8, #0] @ Save calling PC
303 str r6, [r8, #4] @ Save CPSR
304 str r0, [r8, #8] @ Save OLD_R0
308 .macro irq_restore_user_regs
309 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
311 ldr lr, [sp, #S_PC] @ Get PC
312 add sp, sp, #S_FRAME_SIZE
313 subs pc, lr, #4 @ return & move spsr_svc into cpsr
317 ldr r13, _armboot_end @ setup our mode stack
318 add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
321 str lr, [r13] @ save caller lr / spsr
325 mov r13, #MODE_SVC @ prepare SVC-Mode
331 .macro get_irq_stack @ setup IRQ stack
332 ldr sp, IRQ_STACK_START
335 .macro get_fiq_stack @ setup FIQ stack
336 ldr sp, FIQ_STACK_START
343 undefined_instruction:
346 bl do_undefined_instruction
352 bl do_software_interrupt
372 #ifdef CONFIG_USE_IRQ
379 irq_restore_user_regs
384 /* someone ought to write a more effiction fiq_save_user_regs */
387 irq_restore_user_regs
409 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
410 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
411 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
412 bic ip, ip, #0x000f @ ............wcam
413 bic ip, ip, #0x2100 @ ..v....s........
414 mcr p15, 0, ip, c1, c0, 0 @ ctrl register