3 * Author : Hamid Ikdoumi (Atmel)
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <at91rm9200_net.h>
27 #include <asm/mach-types.h>
29 /* ----- Ethernet Buffer definitions ----- */
32 unsigned long addr, size;
35 #define RBF_ADDR 0xfffffffc
36 #define RBF_OWNER (1<<0)
37 #define RBF_WRAP (1<<1)
38 #define RBF_BROADCAST (1<<31)
39 #define RBF_MULTICAST (1<<30)
40 #define RBF_UNICAST (1<<29)
41 #define RBF_EXTERNAL (1<<28)
42 #define RBF_UNKOWN (1<<27)
43 #define RBF_SIZE 0x07ff
44 #define RBF_LOCAL4 (1<<26)
45 #define RBF_LOCAL3 (1<<25)
46 #define RBF_LOCAL2 (1<<24)
47 #define RBF_LOCAL1 (1<<23)
49 #define RBF_FRAMEMAX 64
50 #define RBF_FRAMELEN 0x600
52 #ifdef CONFIG_DRIVER_ETHER
54 #if defined(CONFIG_CMD_NET)
56 /* alignment as per Errata #11 (64 bytes) is insufficient! */
57 rbf_t rbfdt[RBF_FRAMEMAX] __attribute__((aligned(512)));
60 unsigned char rbf_framebuf[RBF_FRAMEMAX][RBF_FRAMELEN]
61 __attribute__((aligned(4)));
63 /* structure to interface the PHY */
68 /*********** EMAC Phy layer Management functions *************************/
71 * at91rm9200_EmacEnableMDIO
73 * Enables the MDIO bit in MAC control register
75 * p_mac - pointer to struct AT91S_EMAC
79 void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
81 /* Mac CTRL reg set for MDIO enable */
82 p_mac->EMAC_CTL |= AT91C_EMAC_MPE; /* Management port enable */
87 * at91rm9200_EmacDisableMDIO
89 * Disables the MDIO bit in MAC control register
91 * p_mac - pointer to struct AT91S_EMAC
95 void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
97 /* Mac CTRL reg set for MDIO disable */
98 p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE; /* Management port disable */
104 * at91rm9200_EmacReadPhy
106 * Reads data from the PHY register
108 * dev - pointer to struct net_device
109 * RegisterAddress - unsigned char
110 * pInput - pointer to value read from register
112 * TRUE - if data read successfully
114 UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
115 unsigned char RegisterAddress,
116 unsigned short *pInput)
118 p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
120 (RegisterAddress << 18) |
121 (AT91C_EMAC_CODE_802_3);
125 *pInput = (unsigned short) p_mac->EMAC_MAN;
133 * at91rm9200_EmacWritePhy
135 * Writes data to the PHY register
137 * dev - pointer to struct net_device
138 * RegisterAddress - unsigned char
139 * pOutput - pointer to value to be written in the register
141 * TRUE - if data read successfully
143 UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
144 unsigned char RegisterAddress,
145 unsigned short *pOutput)
147 p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
148 AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W |
149 (RegisterAddress << 18) | *pOutput;
156 int eth_init (bd_t * bd)
162 p_mac = AT91C_BASE_EMAC;
164 /* PIO Disable Register */
165 *AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER |
166 AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV |
167 AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
168 AT91C_PA7_ETXCK_EREFCK;
170 #ifdef CONFIG_AT91C_USE_RMII
171 *AT91C_PIOB_PDR = AT91C_PB19_ERXCK;
172 *AT91C_PIOB_BSR = AT91C_PB19_ERXCK;
174 *AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
175 AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
176 AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
178 /* Select B Register */
179 *AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
180 AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
181 AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
184 *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */
186 p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */
188 /* Init Ethernet buffers */
189 for (i = 0; i < RBF_FRAMEMAX; i++) {
190 rbfdt[i].addr = (unsigned long)rbf_framebuf[i];
193 rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
196 eth_getenv_enetaddr("ethaddr", enetaddr);
198 /* The CSB337 originally used a version of the MicroMonitor bootloader
199 * which saved Ethernet addresses in the "wrong" order. Operating
200 * systems (like Linux) know this, and apply a workaround. Replicate
201 * that MicroMonitor behavior so we avoid needing to make such OS code
202 * care about which bootloader was used.
204 if (machine_is_csb337()) {
205 p_mac->EMAC_SA2H = (enetaddr[0] << 8) | (enetaddr[1]);
206 p_mac->EMAC_SA2L = (enetaddr[2] << 24) | (enetaddr[3] << 16)
207 | (enetaddr[4] << 8) | (enetaddr[5]);
209 p_mac->EMAC_SA2L = (enetaddr[3] << 24) | (enetaddr[2] << 16)
210 | (enetaddr[1] << 8) | (enetaddr[0]);
211 p_mac->EMAC_SA2H = (enetaddr[5] << 8) | (enetaddr[4]);
214 p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
215 p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
217 p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
220 #ifdef CONFIG_AT91C_USE_RMII
221 p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
224 #if (AT91C_MASTER_CLOCK > 40000000)
225 /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
226 p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64;
229 p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
231 at91rm9200_GetPhyInterface (& PhyOps);
233 if (!PhyOps.IsPhyConnected (p_mac))
234 printf ("PHY not connected!!\n\r");
236 /* MII management start from here */
237 if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
238 if (!(ret = PhyOps.Init (p_mac))) {
239 printf ("MAC: error during MII initialization\n");
243 printf ("No link\n\r");
250 int eth_send (volatile void *packet, int length)
252 while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ));
253 p_mac->EMAC_TAR = (long) packet;
254 p_mac->EMAC_TCR = length;
255 while (p_mac->EMAC_TCR & 0x7ff);
256 p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
264 if (!(rbfp->addr & RBF_OWNER))
267 size = rbfp->size & RBF_SIZE;
268 NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
270 rbfp->addr &= ~RBF_OWNER;
271 if (rbfp->addr & RBF_WRAP)
276 p_mac->EMAC_RSR |= AT91C_EMAC_REC;
285 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
286 int at91rm9200_miiphy_read(char *devname, unsigned char addr,
287 unsigned char reg, unsigned short * value)
289 at91rm9200_EmacEnableMDIO (p_mac);
290 at91rm9200_EmacReadPhy (p_mac, reg, value);
291 at91rm9200_EmacDisableMDIO (p_mac);
295 int at91rm9200_miiphy_write(char *devname, unsigned char addr,
296 unsigned char reg, unsigned short value)
298 at91rm9200_EmacEnableMDIO (p_mac);
299 at91rm9200_EmacWritePhy (p_mac, reg, &value);
300 at91rm9200_EmacDisableMDIO (p_mac);
306 int at91rm9200_miiphy_initialize(bd_t *bis)
308 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
309 miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write);
316 #endif /* CONFIG_DRIVER_ETHER */