3 * Author : Hamid Ikdoumi (Atmel)
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <at91rm9200_net.h>
27 /* ----- Ethernet Buffer definitions ----- */
30 unsigned long addr, size;
33 #define RBF_ADDR 0xfffffffc
34 #define RBF_OWNER (1<<0)
35 #define RBF_WRAP (1<<1)
36 #define RBF_BROADCAST (1<<31)
37 #define RBF_MULTICAST (1<<30)
38 #define RBF_UNICAST (1<<29)
39 #define RBF_EXTERNAL (1<<28)
40 #define RBF_UNKOWN (1<<27)
41 #define RBF_SIZE 0x07ff
42 #define RBF_LOCAL4 (1<<26)
43 #define RBF_LOCAL3 (1<<25)
44 #define RBF_LOCAL2 (1<<24)
45 #define RBF_LOCAL1 (1<<23)
47 /* Emac Buffers in last 512KBytes of SDRAM*/
48 /* Be careful, buffer size is limited to 512KBytes !!! */
49 #define RBF_FRAMEMAX 100
50 /*#define RBF_FRAMEMEM 0x200000 */
51 #define RBF_FRAMEMEM 0x21F80000
52 #define RBF_FRAMELEN 0x600
54 #define RBF_FRAMEBTD RBF_FRAMEMEM
55 #define RBF_FRAMEBUF (RBF_FRAMEMEM + RBF_FRAMEMAX*sizeof(rbf_t))
58 #ifdef CONFIG_DRIVER_ETHER
60 #if (CONFIG_COMMANDS & CFG_CMD_NET)
62 /* structure to interface the PHY */
67 /*********** EMAC Phy layer Management functions *************************/
70 * at91rm9200_EmacEnableMDIO
72 * Enables the MDIO bit in MAC control register
74 * p_mac - pointer to struct AT91S_EMAC
78 void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
80 /* Mac CTRL reg set for MDIO enable */
81 p_mac->EMAC_CTL |= AT91C_EMAC_MPE; /* Management port enable */
86 * at91rm9200_EmacDisableMDIO
88 * Disables the MDIO bit in MAC control register
90 * p_mac - pointer to struct AT91S_EMAC
94 void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
96 /* Mac CTRL reg set for MDIO disable */
97 p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE; /* Management port disable */
103 * at91rm9200_EmacReadPhy
105 * Reads data from the PHY register
107 * dev - pointer to struct net_device
108 * RegisterAddress - unsigned char
109 * pInput - pointer to value read from register
111 * TRUE - if data read successfully
113 UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
114 unsigned char RegisterAddress,
115 unsigned short *pInput)
117 p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
119 (RegisterAddress << 18) |
120 (AT91C_EMAC_CODE_802_3);
124 *pInput = (unsigned short) p_mac->EMAC_MAN;
132 * at91rm9200_EmacWritePhy
134 * Writes data to the PHY register
136 * dev - pointer to struct net_device
137 * RegisterAddress - unsigned char
138 * pOutput - pointer to value to be written in the register
140 * TRUE - if data read successfully
142 UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
143 unsigned char RegisterAddress,
144 unsigned short *pOutput)
146 p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
147 AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W |
148 (RegisterAddress << 18) | *pOutput;
159 int eth_init (bd_t * bd)
164 p_mac = AT91C_BASE_EMAC;
166 /* PIO Disable Register */
167 *AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER |
168 AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV |
169 AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
170 AT91C_PA7_ETXCK_EREFCK;
172 #ifdef CONFIG_AT91C_USE_RMII
173 *AT91C_PIOB_PDR = AT91C_PB19_ERXCK;
174 *AT91C_PIOB_BSR = AT91C_PB19_ERXCK;
176 *AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
177 AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
178 AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
180 /* Select B Register */
181 *AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
182 AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
183 AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
186 *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */
188 p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */
190 /* Init Ehternet buffers */
191 rbfdt = (rbf_t *) RBF_FRAMEBTD;
192 for (i = 0; i < RBF_FRAMEMAX; i++) {
193 rbfdt[i].addr = RBF_FRAMEBUF + RBF_FRAMELEN * i;
196 rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
199 p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16)
200 | (bd->bi_enetaddr[1] << 8) | (bd->bi_enetaddr[0]);
201 p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] << 8) | (bd->bi_enetaddr[4]);
203 p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
204 p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
206 p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
209 #ifdef CONFIG_AT91C_USE_RMII
210 p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
213 #if (AT91C_MASTER_CLOCK > 40000000)
214 /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
215 p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64;
218 p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
220 at91rm9200_GetPhyInterface (& PhyOps);
222 if (!PhyOps.IsPhyConnected (p_mac))
223 printf ("PHY not connected!!\n\r");
225 /* MII management start from here */
226 if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
227 if (!(ret = PhyOps.Init (p_mac))) {
228 printf ("MAC: error during MII initialization\n");
232 printf ("No link\n\r");
239 int eth_send (volatile void *packet, int length)
241 while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ));
242 p_mac->EMAC_TAR = (long) packet;
243 p_mac->EMAC_TCR = length;
244 while (p_mac->EMAC_TCR & 0x7ff);
245 p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
253 if (!(rbfp->addr & RBF_OWNER))
256 size = rbfp->size & RBF_SIZE;
257 NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
259 rbfp->addr &= ~RBF_OWNER;
260 if (rbfp->addr & RBF_WRAP)
265 p_mac->EMAC_RSR |= AT91C_EMAC_REC;
274 #if (CONFIG_COMMANDS & CFG_CMD_MII)
275 int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
277 at91rm9200_EmacEnableMDIO (p_mac);
278 at91rm9200_EmacReadPhy (p_mac, reg, value);
279 at91rm9200_EmacDisableMDIO (p_mac);
283 int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
285 at91rm9200_EmacEnableMDIO (p_mac);
286 at91rm9200_EmacWritePhy (p_mac, reg, &value);
287 at91rm9200_EmacDisableMDIO (p_mac);
290 #endif /* CONFIG_COMMANDS & CFG_CMD_MII */
292 #endif /* CONFIG_COMMANDS & CFG_CMD_NET */
294 #endif /* CONFIG_DRIVER_ETHER */