3 * Author : Hamid Ikdoumi (Atmel)
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <at91rm9200_net.h>
27 /* ----- Ethernet Buffer definitions ----- */
30 unsigned long addr, size;
33 #define RBF_ADDR 0xfffffffc
34 #define RBF_OWNER (1<<0)
35 #define RBF_WRAP (1<<1)
36 #define RBF_BROADCAST (1<<31)
37 #define RBF_MULTICAST (1<<30)
38 #define RBF_UNICAST (1<<29)
39 #define RBF_EXTERNAL (1<<28)
40 #define RBF_UNKOWN (1<<27)
41 #define RBF_SIZE 0x07ff
42 #define RBF_LOCAL4 (1<<26)
43 #define RBF_LOCAL3 (1<<25)
44 #define RBF_LOCAL2 (1<<24)
45 #define RBF_LOCAL1 (1<<23)
47 #define RBF_FRAMEMAX 64
48 #define RBF_FRAMELEN 0x600
50 #ifdef CONFIG_DRIVER_ETHER
52 #if (CONFIG_COMMANDS & CFG_CMD_NET)
54 /* alignment as per Errata #11 (64 bytes) is insufficient! */
55 rbf_t rbfdt[RBF_FRAMEMAX] __attribute((aligned(512)));
58 unsigned char rbf_framebuf[RBF_FRAMEMAX][RBF_FRAMELEN] __attribute((aligned(4)));
60 /* structure to interface the PHY */
65 /*********** EMAC Phy layer Management functions *************************/
68 * at91rm9200_EmacEnableMDIO
70 * Enables the MDIO bit in MAC control register
72 * p_mac - pointer to struct AT91S_EMAC
76 void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
78 /* Mac CTRL reg set for MDIO enable */
79 p_mac->EMAC_CTL |= AT91C_EMAC_MPE; /* Management port enable */
84 * at91rm9200_EmacDisableMDIO
86 * Disables the MDIO bit in MAC control register
88 * p_mac - pointer to struct AT91S_EMAC
92 void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
94 /* Mac CTRL reg set for MDIO disable */
95 p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE; /* Management port disable */
101 * at91rm9200_EmacReadPhy
103 * Reads data from the PHY register
105 * dev - pointer to struct net_device
106 * RegisterAddress - unsigned char
107 * pInput - pointer to value read from register
109 * TRUE - if data read successfully
111 UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
112 unsigned char RegisterAddress,
113 unsigned short *pInput)
115 p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
117 (RegisterAddress << 18) |
118 (AT91C_EMAC_CODE_802_3);
122 *pInput = (unsigned short) p_mac->EMAC_MAN;
130 * at91rm9200_EmacWritePhy
132 * Writes data to the PHY register
134 * dev - pointer to struct net_device
135 * RegisterAddress - unsigned char
136 * pOutput - pointer to value to be written in the register
138 * TRUE - if data read successfully
140 UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
141 unsigned char RegisterAddress,
142 unsigned short *pOutput)
144 p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
145 AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W |
146 (RegisterAddress << 18) | *pOutput;
154 int eth_init (bd_t * bd)
159 p_mac = AT91C_BASE_EMAC;
161 /* PIO Disable Register */
162 *AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER |
163 AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV |
164 AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
165 AT91C_PA7_ETXCK_EREFCK;
167 #ifdef CONFIG_AT91C_USE_RMII
168 *AT91C_PIOB_PDR = AT91C_PB19_ERXCK;
169 *AT91C_PIOB_BSR = AT91C_PB19_ERXCK;
171 *AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
172 AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
173 AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
175 /* Select B Register */
176 *AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
177 AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
178 AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
181 *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */
183 p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */
185 /* Init Ehternet buffers */
186 for (i = 0; i < RBF_FRAMEMAX; i++) {
187 rbfdt[i].addr = (unsigned long)rbf_framebuf[i];
190 rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
193 p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16)
194 | (bd->bi_enetaddr[1] << 8) | (bd->bi_enetaddr[0]);
195 p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] << 8) | (bd->bi_enetaddr[4]);
197 p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
198 p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
200 p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
203 #ifdef CONFIG_AT91C_USE_RMII
204 p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
207 #if (AT91C_MASTER_CLOCK > 40000000)
208 /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
209 p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64;
212 p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
214 at91rm9200_GetPhyInterface (& PhyOps);
216 if (!PhyOps.IsPhyConnected (p_mac))
217 printf ("PHY not connected!!\n\r");
219 /* MII management start from here */
220 if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
221 if (!(ret = PhyOps.Init (p_mac))) {
222 printf ("MAC: error during MII initialization\n");
226 printf ("No link\n\r");
233 int eth_send (volatile void *packet, int length)
235 while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ));
236 p_mac->EMAC_TAR = (long) packet;
237 p_mac->EMAC_TCR = length;
238 while (p_mac->EMAC_TCR & 0x7ff);
239 p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
247 if (!(rbfp->addr & RBF_OWNER))
250 size = rbfp->size & RBF_SIZE;
251 NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
253 rbfp->addr &= ~RBF_OWNER;
254 if (rbfp->addr & RBF_WRAP)
259 p_mac->EMAC_RSR |= AT91C_EMAC_REC;
268 #if (CONFIG_COMMANDS & CFG_CMD_MII)
269 int miiphy_read(unsigned char addr, unsigned char reg, unsigned short * value)
271 at91rm9200_EmacEnableMDIO (p_mac);
272 at91rm9200_EmacReadPhy (p_mac, reg, value);
273 at91rm9200_EmacDisableMDIO (p_mac);
277 int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
279 at91rm9200_EmacEnableMDIO (p_mac);
280 at91rm9200_EmacWritePhy (p_mac, reg, &value);
281 at91rm9200_EmacDisableMDIO (p_mac);
284 #endif /* CONFIG_COMMANDS & CFG_CMD_MII */
286 #endif /* CONFIG_COMMANDS & CFG_CMD_NET */
288 #endif /* CONFIG_DRIVER_ETHER */