2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 *************************************************************************
33 * Jump vector table as in table 3.1 in [1]
35 *************************************************************************
41 ldr pc, _undefined_instruction
42 ldr pc, _software_interrupt
43 ldr pc, _prefetch_abort
49 _undefined_instruction: .word undefined_instruction
50 _software_interrupt: .word software_interrupt
51 _prefetch_abort: .word prefetch_abort
52 _data_abort: .word data_abort
53 _not_used: .word not_used
57 .balignl 16,0xdeadbeef
61 *************************************************************************
63 * Startup Code (called from the ARM reset exception vector)
65 * do important init only if we don't start from memory!
66 * relocate armboot to ram
68 * jump to second stage
70 *************************************************************************
81 * These are defined in the board-specific linker script.
92 /* IRQ stack memory (calculated at run-time) */
93 .globl IRQ_STACK_START
97 /* IRQ stack memory (calculated at run-time) */
98 .globl FIQ_STACK_START
105 * the actual start code
110 * set the cpu to SVC32 mode
120 #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
122 * relocate exception table
134 #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
135 /* turn off the watchdog */
137 # if defined(CONFIG_S3C2400)
138 # define pWTCON 0x15300000
139 # define INTMSK 0x14400008 /* Interupt-Controller base addresses */
140 # define CLKDIVN 0x14800014 /* clock divisor register */
142 # define pWTCON 0x53000000
143 # define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
144 # define INTSUBMSK 0x4A00001C
145 # define CLKDIVN 0x4C000014 /* clock divisor register */
153 * mask all IRQs by setting all bits in the INTMR - default
158 # if defined(CONFIG_S3C2410)
164 /* FCLK:HCLK:PCLK = 1:2:4 */
165 /* default FCLK is 120 MHz ! */
169 #endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
172 * we do sys-critical inits only at reboot,
173 * not when booting from ram!
175 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
179 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
180 relocate: /* relocate U-Boot to RAM */
181 adr r0, _start /* r0 <- current position of code */
182 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
183 cmp r0, r1 /* don't reloc during debug */
186 ldr r2, _armboot_start
188 sub r2, r3, r2 /* r2 <- size of armboot */
189 add r2, r0, r2 /* r2 <- source end address */
192 ldmia r0!, {r3-r10} /* copy from source address [r0] */
193 stmia r1!, {r3-r10} /* copy to target address [r1] */
194 cmp r0, r2 /* until source end addreee [r2] */
196 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
198 /* Set up the stack */
200 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
201 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
202 sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
203 #ifdef CONFIG_USE_IRQ
204 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
206 sub sp, r0, #12 /* leave 3 words for abort-stack */
209 ldr r0, _bss_start /* find start of bss segment */
210 ldr r1, _bss_end /* stop here */
211 mov r2, #0x00000000 /* clear */
213 clbss_l:str r2, [r0] /* clear loop... */
218 ldr pc, _start_armboot
220 _start_armboot: .word start_armboot
224 *************************************************************************
226 * CPU_init_critical registers
228 * setup important registers
229 * setup memory timing
231 *************************************************************************
235 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
238 * flush v4 I/D caches
241 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
242 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
245 * disable MMU stuff and caches
247 mrc p15, 0, r0, c1, c0, 0
248 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
249 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
250 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
251 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
252 mcr p15, 0, r0, c1, c0, 0
255 * before relocating, we have to setup RAM timing
256 * because memory timing is board-dependend, you will
257 * find a lowlevel_init.S in your board directory.
265 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
268 *************************************************************************
272 *************************************************************************
278 #define S_FRAME_SIZE 72
300 #define MODE_SVC 0x13
304 * use bad_save_user_regs for abort/prefetch/undef/swi ...
305 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
308 .macro bad_save_user_regs
309 sub sp, sp, #S_FRAME_SIZE
310 stmia sp, {r0 - r12} @ Calling r0-r12
311 ldr r2, _armboot_start
312 sub r2, r2, #(CONFIG_STACKSIZE)
313 sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
314 sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
315 ldmia r2, {r2 - r3} @ get pc, cpsr
316 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
320 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
324 .macro irq_save_user_regs
325 sub sp, sp, #S_FRAME_SIZE
326 stmia sp, {r0 - r12} @ Calling r0-r12
328 stmdb r7, {sp, lr}^ @ Calling SP, LR
329 str lr, [r7, #0] @ Save calling PC
331 str r6, [r7, #4] @ Save CPSR
332 str r0, [r7, #8] @ Save OLD_R0
336 .macro irq_restore_user_regs
337 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
339 ldr lr, [sp, #S_PC] @ Get PC
340 add sp, sp, #S_FRAME_SIZE
341 subs pc, lr, #4 @ return & move spsr_svc into cpsr
345 ldr r13, _armboot_start @ setup our mode stack
346 sub r13, r13, #(CONFIG_STACKSIZE)
347 sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
348 sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
350 str lr, [r13] @ save caller lr / spsr
354 mov r13, #MODE_SVC @ prepare SVC-Mode
361 .macro get_irq_stack @ setup IRQ stack
362 ldr sp, IRQ_STACK_START
365 .macro get_fiq_stack @ setup FIQ stack
366 ldr sp, FIQ_STACK_START
373 undefined_instruction:
376 bl do_undefined_instruction
382 bl do_software_interrupt
402 #ifdef CONFIG_USE_IRQ
409 irq_restore_user_regs
414 /* someone ought to write a more effiction fiq_save_user_regs */
417 irq_restore_user_regs