2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 *************************************************************************
35 * Jump vector table as in table 3.1 in [1]
37 *************************************************************************
43 ldr pc, _undefined_instruction
44 ldr pc, _software_interrupt
45 ldr pc, _prefetch_abort
51 _undefined_instruction: .word undefined_instruction
52 _software_interrupt: .word software_interrupt
53 _prefetch_abort: .word prefetch_abort
54 _data_abort: .word data_abort
55 _not_used: .word not_used
59 .balignl 16,0xdeadbeef
63 *************************************************************************
65 * Startup Code (reset vector)
67 * do important init only if we don't start from memory!
68 * relocate armboot to ram
70 * jump to second stage
72 *************************************************************************
83 * Note: _armboot_end_data and _armboot_end are defined
84 * by the (board-dependent) linker script.
85 * _armboot_end_data is the first usable FLASH address after armboot
87 .globl _armboot_end_data
89 .word armboot_end_data
95 /* IRQ stack memory (calculated at run-time) */
96 .globl IRQ_STACK_START
100 /* IRQ stack memory (calculated at run-time) */
101 .globl FIQ_STACK_START
108 * the actual reset code
113 * set the cpu to SVC32 mode
120 /* turn off the watchdog */
121 #if defined(CONFIG_S3C2400)
122 #define pWTCON 0x15300000
123 /* Interupt-Controller base addresses */
124 #define INTMSK 0x14400008
125 /* clock divisor register */
126 #define CLKDIVN 0x14800014
127 #elif defined(CONFIG_S3C2410)
128 #define pWTCON 0x53000000
129 /* Interupt-Controller base addresses */
130 #define INTMSK 0x4A000008
131 #define INTSUBMSK 0x4A00001C
132 /* clock divisor register */
133 #define CLKDIVN 0x4C000014
141 * mask all IRQs by setting all bits in the INTMR - default
146 #if defined(CONFIG_S3C2410)
152 /* FCLK:HCLK:PCLK = 1:2:4 */
153 /* default FCLK is 120 MHz ! */
159 * we do sys-critical inits only at reboot,
160 * not when booting from ram!
162 #ifdef CONFIG_INIT_CRITICAL
166 relocate: /* relocate U-Boot to RAM */
167 adr r0, _start /* r0 <- current position of code */
168 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
169 cmp r0, r1 /* don't reloc during debug */
172 ldr r2, _armboot_start
174 sub r2, r3, r2 /* r2 <- size of armboot */
175 add r2, r0, r2 /* r2 <- source end address */
178 ldmia r0!, {r3-r10} /* copy from source address [r0] */
179 stmia r1!, {r3-r10} /* copy to target address [r1] */
180 cmp r0, r2 /* until source end addreee [r2] */
183 /* Set up the stack */
185 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
186 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
187 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
188 #ifdef CONFIG_USE_IRQ
189 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
191 sub sp, r0, #12 /* leave 3 words for abort-stack */
194 /* try doing this stuff after the relocation */
200 * mask all IRQs by setting all bits in the INTMR - default
206 /* FCLK:HCLK:PCLK = 1:2:4 */
207 /* default FCLK is 120 MHz ! */
211 /* END stuff after relocation */
214 ldr pc, _start_armboot
216 _start_armboot: .word start_armboot
220 *************************************************************************
222 * CPU_init_critical registers
224 * setup important registers
225 * setup memory timing
227 *************************************************************************
233 * flush v4 I/D caches
236 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
237 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
240 * disable MMU stuff and caches
242 mrc p15, 0, r0, c1, c0, 0
243 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
244 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
245 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
246 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
247 mcr p15, 0, r0, c1, c0, 0
251 * before relocating, we have to setup RAM timing
252 * because memory timing is board-dependend, you will
253 * find a memsetup.S in your board directory.
263 *************************************************************************
267 *************************************************************************
273 #define S_FRAME_SIZE 72
295 #define MODE_SVC 0x13
299 * use bad_save_user_regs for abort/prefetch/undef/swi ...
300 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
303 .macro bad_save_user_regs
304 sub sp, sp, #S_FRAME_SIZE
305 stmia sp, {r0 - r12} @ Calling r0-r12
307 add r2, r2, #CONFIG_STACKSIZE
309 ldmia r2, {r2 - r3} @ get pc, cpsr
310 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
314 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
318 .macro irq_save_user_regs
319 sub sp, sp, #S_FRAME_SIZE
320 stmia sp, {r0 - r12} @ Calling r0-r12
322 stmdb r8, {sp, lr}^ @ Calling SP, LR
323 str lr, [r8, #0] @ Save calling PC
325 str r6, [r8, #4] @ Save CPSR
326 str r0, [r8, #8] @ Save OLD_R0
330 .macro irq_restore_user_regs
331 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
333 ldr lr, [sp, #S_PC] @ Get PC
334 add sp, sp, #S_FRAME_SIZE
335 subs pc, lr, #4 @ return & move spsr_svc into cpsr
339 ldr r13, _armboot_end @ setup our mode stack
340 add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
343 str lr, [r13] @ save caller lr / spsr
347 mov r13, #MODE_SVC @ prepare SVC-Mode
354 .macro get_irq_stack @ setup IRQ stack
355 ldr sp, IRQ_STACK_START
358 .macro get_fiq_stack @ setup FIQ stack
359 ldr sp, FIQ_STACK_START
366 undefined_instruction:
369 bl do_undefined_instruction
375 bl do_software_interrupt
395 #ifdef CONFIG_USE_IRQ
402 irq_restore_user_regs
407 /* someone ought to write a more effiction fiq_save_user_regs */
410 irq_restore_user_regs
431 #ifdef CONFIG_S3C2400
432 bl disable_interrupts
438 /* Disable watchdog */
441 /* Initialize watchdog timer count register */
444 /* Enable watchdog timer; assert reset at timer timeout */
453 #else /* ! CONFIG_S3C2400 */
455 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
456 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
457 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
458 bic ip, ip, #0x000f @ ............wcam
459 bic ip, ip, #0x2100 @ ..v....s........
460 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
462 #endif /* CONFIG_S3C2400 */