2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
7 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
8 * esd electronic system design gmbh <www.esd.eu>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/at91_common.h>
31 #include <asm/arch/at91_pmc.h>
32 #include <asm/arch/gpio.h>
33 #include <asm/arch/io.h>
35 void at91_serial0_hw_init(void)
37 at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */
38 at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */
39 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US0);
42 void at91_serial1_hw_init(void)
44 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
45 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
46 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US1);
49 void at91_serial2_hw_init(void)
51 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
52 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
53 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US2);
56 void at91_serial3_hw_init(void)
58 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
59 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
60 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
63 void at91_serial_hw_init(void)
66 at91_serial0_hw_init();
70 at91_serial1_hw_init();
74 at91_serial2_hw_init();
77 #ifdef CONFIG_USART3 /* DBGU */
78 at91_serial3_hw_init();
82 #ifdef CONFIG_HAS_DATAFLASH
83 void at91_spi0_hw_init(unsigned long cs_mask)
85 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
86 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
87 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
90 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0);
92 if (cs_mask & (1 << 0)) {
93 at91_set_B_periph(AT91_PIN_PA5, 1);
95 if (cs_mask & (1 << 1)) {
96 at91_set_B_periph(AT91_PIN_PA3, 1);
98 if (cs_mask & (1 << 2)) {
99 at91_set_B_periph(AT91_PIN_PD0, 1);
101 if (cs_mask & (1 << 3)) {
102 at91_set_B_periph(AT91_PIN_PD1, 1);
104 if (cs_mask & (1 << 4)) {
105 at91_set_gpio_output(AT91_PIN_PA5, 1);
107 if (cs_mask & (1 << 5)) {
108 at91_set_gpio_output(AT91_PIN_PA3, 1);
110 if (cs_mask & (1 << 6)) {
111 at91_set_gpio_output(AT91_PIN_PD0, 1);
113 if (cs_mask & (1 << 7)) {
114 at91_set_gpio_output(AT91_PIN_PD1, 1);
118 void at91_spi1_hw_init(unsigned long cs_mask)
120 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
121 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
122 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
125 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI1);
127 if (cs_mask & (1 << 0)) {
128 at91_set_A_periph(AT91_PIN_PB15, 1);
130 if (cs_mask & (1 << 1)) {
131 at91_set_A_periph(AT91_PIN_PB16, 1);
133 if (cs_mask & (1 << 2)) {
134 at91_set_A_periph(AT91_PIN_PB17, 1);
136 if (cs_mask & (1 << 3)) {
137 at91_set_A_periph(AT91_PIN_PB18, 1);
139 if (cs_mask & (1 << 4)) {
140 at91_set_gpio_output(AT91_PIN_PB15, 1);
142 if (cs_mask & (1 << 5)) {
143 at91_set_gpio_output(AT91_PIN_PB16, 1);
145 if (cs_mask & (1 << 6)) {
146 at91_set_gpio_output(AT91_PIN_PB17, 1);
148 if (cs_mask & (1 << 7)) {
149 at91_set_gpio_output(AT91_PIN_PB18, 1);
156 void at91_macb_hw_init(void)
158 at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */
159 at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */
160 at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */
161 at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */
162 at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */
163 at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */
164 at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */
165 at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */
166 at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */
167 at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */
170 at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */
171 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
172 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
173 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
174 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
175 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
176 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
177 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
182 #ifdef CONFIG_AT91_CAN
183 void at91_can_hw_init(void)
185 at91_set_A_periph(AT91_PIN_PA12, 0); /* CAN_TX */
186 at91_set_A_periph(AT91_PIN_PA13, 1); /* CAN_RX */
189 at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_CAN);