2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/at91_common.h>
27 #include <asm/arch/at91_pmc.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/io.h>
31 void at91_serial0_hw_init(void)
33 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
34 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
35 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
38 void at91_serial1_hw_init(void)
40 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
41 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
42 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
45 void at91_serial2_hw_init(void)
47 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
48 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
49 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
52 void at91_serial3_hw_init(void)
54 at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
55 at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
56 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
59 void at91_serial_hw_init(void)
62 at91_serial0_hw_init();
66 at91_serial1_hw_init();
70 at91_serial2_hw_init();
73 #ifdef CONFIG_USART3 /* DBGU */
74 at91_serial3_hw_init();
78 #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
79 void at91_spi0_hw_init(unsigned long cs_mask)
81 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
82 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
83 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
86 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
88 if (cs_mask & (1 << 0)) {
89 at91_set_A_periph(AT91_PIN_PA3, 1);
91 if (cs_mask & (1 << 1)) {
92 at91_set_B_periph(AT91_PIN_PC11, 1);
94 if (cs_mask & (1 << 2)) {
95 at91_set_B_periph(AT91_PIN_PC16, 1);
97 if (cs_mask & (1 << 3)) {
98 at91_set_B_periph(AT91_PIN_PC17, 1);
100 if (cs_mask & (1 << 4)) {
101 at91_set_gpio_output(AT91_PIN_PA3, 1);
103 if (cs_mask & (1 << 5)) {
104 at91_set_gpio_output(AT91_PIN_PC11, 1);
106 if (cs_mask & (1 << 6)) {
107 at91_set_gpio_output(AT91_PIN_PC16, 1);
109 if (cs_mask & (1 << 7)) {
110 at91_set_gpio_output(AT91_PIN_PC17, 1);
114 void at91_spi1_hw_init(unsigned long cs_mask)
116 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */
117 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */
118 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */
121 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI1);
123 if (cs_mask & (1 << 0)) {
124 at91_set_A_periph(AT91_PIN_PB3, 1);
126 if (cs_mask & (1 << 1)) {
127 at91_set_B_periph(AT91_PIN_PC5, 1);
129 if (cs_mask & (1 << 2)) {
130 at91_set_B_periph(AT91_PIN_PC4, 1);
132 if (cs_mask & (1 << 3)) {
133 at91_set_gpio_output(AT91_PIN_PC3, 1);
135 if (cs_mask & (1 << 4)) {
136 at91_set_gpio_output(AT91_PIN_PB3, 1);
138 if (cs_mask & (1 << 5)) {
139 at91_set_gpio_output(AT91_PIN_PC5, 1);
141 if (cs_mask & (1 << 6)) {
142 at91_set_gpio_output(AT91_PIN_PC4, 1);
144 if (cs_mask & (1 << 7)) {
145 at91_set_gpio_output(AT91_PIN_PC3, 1);
151 void at91_macb_hw_init(void)
153 at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
154 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
155 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
156 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
157 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
158 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
159 at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
160 at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
161 at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
162 at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
165 at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
166 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
167 at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
168 at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
169 at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
170 #if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260)
172 * use PA10, PA11 for ETX2, ETX3.
173 * PA23 and PA24 are for TWI EEPROM
175 at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */
176 at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */
178 at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
179 at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
181 at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */