2 * TI DaVinci (TMS320DM644x) I2C driver.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * --------------------------------------------------------
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #ifdef CONFIG_DRIVER_DAVINCI_I2C
32 #include <asm/arch/hardware.h>
33 #include <asm/arch/i2c_defs.h>
35 #define CHECK_NACK() \
37 if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
44 static int wait_for_bus(void)
48 REG(I2C_STAT) = 0xffff;
50 for (timeout = 0; timeout < 10; timeout++) {
51 if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) {
52 REG(I2C_STAT) = 0xffff;
60 REG(I2C_STAT) = 0xffff;
65 static int poll_i2c_irq(int mask)
69 for (timeout = 0; timeout < 10; timeout++) {
77 REG(I2C_STAT) = 0xffff;
78 return(stat | I2C_TIMEOUT);
87 if (!(REG(I2C_STAT) & I2C_STAT_RRDY))
91 REG(I2C_STAT) = I2C_STAT_RRDY;
97 void i2c_init(int speed, int slaveadd)
101 if (REG(I2C_CON) & I2C_CON_EN) {
107 div = (CFG_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */
108 REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */
109 REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */
110 REG(I2C_SCLH) = div - REG(I2C_SCLL);
112 REG(I2C_OA) = slaveadd;
115 /* Interrupts must be enabled or I2C module won't work */
116 REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
117 I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
119 /* Now enable I2C controller (get it out of reset) */
120 REG(I2C_CON) = I2C_CON_EN;
126 int i2c_probe(u_int8_t chip)
130 if (chip == REG(I2C_OA)) {
135 if (wait_for_bus()) {return(1);}
137 /* try to read one byte from current (or only) address */
140 REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP);
143 if (!(REG(I2C_STAT) & I2C_STAT_NACK)) {
146 REG(I2C_STAT) = 0xffff;
148 REG(I2C_STAT) = 0xffff;
149 REG(I2C_CON) |= I2C_CON_STP;
151 if (wait_for_bus()) {return(1);}
155 REG(I2C_STAT) = 0xffff;
161 int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
166 if ((alen < 0) || (alen > 2)) {
167 printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
171 if (wait_for_bus()) {return(1);}
174 /* Start address phase */
175 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
180 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
186 /* Send address MSByte */
187 if (tmp & I2C_STAT_XRDY) {
188 REG(I2C_DXR) = (addr >> 8) & 0xff;
194 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
197 /* No break, fall through */
199 /* Send address LSByte */
200 if (tmp & I2C_STAT_XRDY) {
201 REG(I2C_DXR) = addr & 0xff;
207 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY);
211 if (!(tmp & I2C_STAT_ARDY)) {
218 /* Address phase is over, now read 'len' bytes and stop */
219 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
220 REG(I2C_CNT) = len & 0xffff;
224 for (i = 0; i < len; i++) {
225 tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR);
229 if (tmp & I2C_STAT_RRDY) {
230 buf[i] = REG(I2C_DRR);
237 tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
241 if (!(tmp & I2C_STAT_SCD)) {
247 REG(I2C_STAT) = 0xffff;
255 int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
260 if ((alen < 0) || (alen > 2)) {
261 printf("%s(): bogus address length %x\n", __FUNCTION__, alen);
265 printf("%s(): bogus length %x\n", __FUNCTION__, len);
269 if (wait_for_bus()) {return(1);}
271 /* Start address phase */
272 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP;
273 REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen;
279 /* Send address MSByte */
280 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
284 if (tmp & I2C_STAT_XRDY) {
285 REG(I2C_DXR) = (addr >> 8) & 0xff;
290 /* No break, fall through */
292 /* Send address LSByte */
293 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
297 if (tmp & I2C_STAT_XRDY) {
298 REG(I2C_DXR) = addr & 0xff;
305 for (i = 0; i < len; i++) {
306 tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK);
310 if (tmp & I2C_STAT_XRDY) {
311 REG(I2C_DXR) = buf[i];
317 tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK);
321 if (!(tmp & I2C_STAT_SCD)) {
327 REG(I2C_STAT) = 0xffff;
335 u_int8_t i2c_reg_read(u_int8_t chip, u_int8_t reg)
339 i2c_read(chip, reg, 1, &tmp, 1);
344 void i2c_reg_write(u_int8_t chip, u_int8_t reg, u_int8_t val)
348 i2c_write(chip, reg, 1, &tmp, 1);
351 #endif /* CONFIG_DRIVER_DAVINCI_I2C */