3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
11 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <configs/omap1510.h>
36 #include <asm/proc-armv/ptrace.h>
38 extern void reset_cpu(ulong addr);
39 #define TIMER_LOAD_VAL 0xffffffff
41 /* macro to read the 32 bit timer */
42 #define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
45 /* enable IRQ interrupts */
46 void enable_interrupts (void)
49 __asm__ __volatile__("mrs %0, cpsr\n"
57 * disable IRQ/FIQ interrupts
58 * returns true if interrupts had been enabled before we disabled them
60 int disable_interrupts (void)
62 unsigned long old,temp;
63 __asm__ __volatile__("mrs %0, cpsr\n"
66 : "=r" (old), "=r" (temp)
68 return (old & 0x80) == 0;
71 void enable_interrupts (void)
75 int disable_interrupts (void)
85 panic ("Resetting CPU ...\n");
89 void show_regs (struct pt_regs *regs)
92 const char *processor_modes[] = {
93 "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
94 "UK4_26", "UK5_26", "UK6_26", "UK7_26",
95 "UK8_26", "UK9_26", "UK10_26", "UK11_26",
96 "UK12_26", "UK13_26", "UK14_26", "UK15_26",
97 "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
98 "UK4_32", "UK5_32", "UK6_32", "ABT_32",
99 "UK8_32", "UK9_32", "UK10_32", "UND_32",
100 "UK12_32", "UK13_32", "UK14_32", "SYS_32",
103 flags = condition_codes (regs);
105 printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
106 "sp : %08lx ip : %08lx fp : %08lx\n",
107 instruction_pointer (regs),
108 regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
109 printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
110 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
111 printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
112 regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
113 printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
114 regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
115 printf ("Flags: %c%c%c%c",
116 flags & CC_N_BIT ? 'N' : 'n',
117 flags & CC_Z_BIT ? 'Z' : 'z',
118 flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
119 printf (" IRQs %s FIQs %s Mode %s%s\n",
120 interrupts_enabled (regs) ? "on" : "off",
121 fast_interrupts_enabled (regs) ? "on" : "off",
122 processor_modes[processor_mode (regs)],
123 thumb_mode (regs) ? " (T)" : "");
126 void do_undefined_instruction (struct pt_regs *pt_regs)
128 printf ("undefined instruction\n");
133 void do_software_interrupt (struct pt_regs *pt_regs)
135 printf ("software interrupt\n");
140 void do_prefetch_abort (struct pt_regs *pt_regs)
142 printf ("prefetch abort\n");
147 void do_data_abort (struct pt_regs *pt_regs)
149 printf ("data abort\n");
154 void do_not_used (struct pt_regs *pt_regs)
156 printf ("not used\n");
161 void do_fiq (struct pt_regs *pt_regs)
163 printf ("fast interrupt request\n");
168 void do_irq (struct pt_regs *pt_regs)
170 printf ("interrupt request\n");
175 static ulong timestamp;
176 static ulong lastdec;
178 /* nothing really to do with interrupts, just starts up a counter. */
179 int interrupt_init (void)
183 *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
184 val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE |
185 (CFG_PVT << MPUTIM_PTV_BIT);
186 *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
191 * timer without interrupts
194 void reset_timer (void)
196 reset_timer_masked ();
199 ulong get_timer (ulong base)
201 return get_timer_masked () - base;
204 void set_timer (ulong t)
209 /* very rough timer... */
210 void udelay (unsigned long usec)
212 #ifdef CONFIG_INNOVATOROMAP1610
213 #define LOOPS_PER_MSEC 100 /* tuned on omap1610 */
214 volatile int i, time_remaining = LOOPS_PER_MSEC * usec;
216 for (i = time_remaining; i > 0; i--) {
224 tmo += get_timer (0);
225 while (get_timer_masked () < tmo)
230 void reset_timer_masked (void)
233 lastdec = READ_TIMER;
237 ulong get_timer_masked (void)
239 ulong now = READ_TIMER; /* current tick value */
241 if (lastdec >= now) { /* did I roll (rem decrementer) */
243 /* record amount of time since last check */
244 timestamp += lastdec - now;
246 /* we have an overflow ... */
247 timestamp += lastdec + TIMER_LOAD_VAL - now;
254 void udelay_masked (unsigned long usec)
256 #ifdef CONFIG_INNOVATOROMAP1610
257 #define LOOPS_PER_MSEC 100 /* tuned on omap1610 */
258 volatile int i, time_remaining = LOOPS_PER_MSEC*usec;
259 for (i=time_remaining; i>0; i--) { }
268 reset_timer_masked ();
270 while (get_timer_masked () < tmo)
276 * This function is derived from PowerPC code (read timebase as long long).
277 * On ARM it just returns the timer value.
279 unsigned long long get_ticks(void)
285 * This function is derived from PowerPC code (timebase clock frequency).
286 * On ARM it returns the number of timer ticks per second.
288 ulong get_tbclk (void)