2 * Copyright (C) 2009 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Heungjun Kim <riverful.kim@samsung.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/clock.h>
39 #ifndef CONFIG_SYS_CLK_FREQ_C100
40 #define CONFIG_SYS_CLK_FREQ_C100 12000000
42 #ifndef CONFIG_SYS_CLK_FREQ_C110
43 #define CONFIG_SYS_CLK_FREQ_C110 24000000
46 unsigned long (*get_pclk)(void);
47 unsigned long (*get_arm_clk)(void);
48 unsigned long (*get_pll_clk)(int);
50 /* s5pc110: return pll clock frequency */
51 static unsigned long s5pc100_get_pll_clk(int pllreg)
53 struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
54 unsigned long r, m, p, s, mask, fout;
59 r = readl(&clk->apll_con);
62 r = readl(&clk->mpll_con);
65 r = readl(&clk->epll_con);
68 r = readl(&clk->hpll_con);
71 printf("Unsupported PLL (%d)\n", pllreg);
76 * APLL_CON: MIDV [25:16]
77 * MPLL_CON: MIDV [23:16]
78 * EPLL_CON: MIDV [23:16]
79 * HPLL_CON: MIDV [23:16]
93 /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
94 freq = CONFIG_SYS_CLK_FREQ_C100;
95 fout = m * (freq / (p * (1 << s)));
100 /* s5pc100: return pll clock frequency */
101 static unsigned long s5pc110_get_pll_clk(int pllreg)
103 struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
104 unsigned long r, m, p, s, mask, fout;
109 r = readl(&clk->apll_con);
112 r = readl(&clk->mpll_con);
115 r = readl(&clk->epll_con);
118 r = readl(&clk->vpll_con);
121 printf("Unsupported PLL (%d)\n", pllreg);
126 * APLL_CON: MIDV [25:16]
127 * MPLL_CON: MIDV [25:16]
128 * EPLL_CON: MIDV [24:16]
129 * VPLL_CON: MIDV [24:16]
131 if (pllreg == APLL || pllreg == MPLL)
136 m = (r >> 16) & mask;
143 freq = CONFIG_SYS_CLK_FREQ_C110;
144 if (pllreg == APLL) {
147 /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
148 fout = m * (freq / (p * (1 << (s - 1))));
150 /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
151 fout = m * (freq / (p * (1 << s)));
156 /* s5pc110: return ARM clock frequency */
157 static unsigned long s5pc110_get_arm_clk(void)
159 struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
161 unsigned long dout_apll, armclk;
162 unsigned int apll_ratio;
164 div = readl(&clk->div0);
166 /* APLL_RATIO: [2:0] */
167 apll_ratio = div & 0x7;
169 dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
175 /* s5pc100: return ARM clock frequency */
176 static unsigned long s5pc100_get_arm_clk(void)
178 struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
180 unsigned long dout_apll, armclk;
181 unsigned int apll_ratio, arm_ratio;
183 div = readl(&clk->div0);
185 /* ARM_RATIO: [6:4] */
186 arm_ratio = (div >> 4) & 0x7;
187 /* APLL_RATIO: [0] */
188 apll_ratio = div & 0x1;
190 dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
191 armclk = dout_apll / (arm_ratio + 1);
196 /* s5pc100: return HCLKD0 frequency */
197 static unsigned long get_hclk(void)
199 struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
200 unsigned long hclkd0;
201 uint div, d0_bus_ratio;
203 div = readl(&clk->div0);
204 /* D0_BUS_RATIO: [10:8] */
205 d0_bus_ratio = (div >> 8) & 0x7;
207 hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
212 /* s5pc100: return PCLKD1 frequency */
213 static unsigned long get_pclkd1(void)
215 struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
216 unsigned long d1_bus, pclkd1;
217 uint div, d1_bus_ratio, pclkd1_ratio;
219 div = readl(&clk->div0);
220 /* D1_BUS_RATIO: [14:12] */
221 d1_bus_ratio = (div >> 12) & 0x7;
222 /* PCLKD1_RATIO: [18:16] */
223 pclkd1_ratio = (div >> 16) & 0x7;
226 d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
227 pclkd1 = d1_bus / (pclkd1_ratio + 1);
232 /* s5pc110: return HCLKs frequency */
233 static unsigned long get_hclk_sys(int dom)
235 struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
239 unsigned int hclk_sys_ratio;
244 div = readl(&clk->div0);
247 * HCLK_MSYS_RATIO: [10:8]
248 * HCLK_DSYS_RATIO: [19:16]
249 * HCLK_PSYS_RATIO: [27:24]
251 offset = 8 + (dom << 0x3);
253 hclk_sys_ratio = (div >> offset) & 0xf;
255 hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
260 /* s5pc110: return PCLKs frequency */
261 static unsigned long get_pclk_sys(int dom)
263 struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
267 unsigned int pclk_sys_ratio;
269 div = readl(&clk->div0);
272 * PCLK_MSYS_RATIO: [14:12]
273 * PCLK_DSYS_RATIO: [22:20]
274 * PCLK_PSYS_RATIO: [30:28]
276 offset = 12 + (dom << 0x3);
278 pclk_sys_ratio = (div >> offset) & 0x7;
280 pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
285 /* s5pc110: return peripheral clock frequency */
286 static unsigned long s5pc110_get_pclk(void)
288 return get_pclk_sys(CLK_P);
291 /* s5pc100: return peripheral clock frequency */
292 static unsigned long s5pc100_get_pclk(void)
297 void s5pc1xx_clock_init(void)
299 if (cpu_is_s5pc110()) {
300 get_pll_clk = s5pc110_get_pll_clk;
301 get_arm_clk = s5pc110_get_arm_clk;
302 get_pclk = s5pc110_get_pclk;
304 get_pll_clk = s5pc100_get_pll_clk;
305 get_arm_clk = s5pc100_get_arm_clk;
306 get_pclk = s5pc100_get_pclk;