2 * Copyright (C) 2005-2006 Atmel Corporation
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/sdram.h>
28 #include <asm/arch/platform.h>
33 const struct device *hebi;
37 static struct hsdramc hsdramc;
39 unsigned long sdram_init(const struct sdram_info *info)
41 unsigned long *sdram = (unsigned long *)uncached(info->phys_addr);
42 unsigned long sdram_size;
47 hsdramc.hebi = get_device(DEVICE_HEBI);
51 /* FIXME: Both of these lines are complete hacks */
52 hsdramc.regs = hsdramc.hebi->regs + 0x400;
53 bus_hz = pm_get_clock_freq(hsdramc.hebi->resource[0].u.clock.id);
57 tmp = (HSDRAMC1_BF(NC, info->col_bits - 8)
58 | HSDRAMC1_BF(NR, info->row_bits - 11)
59 | HSDRAMC1_BF(NB, info->bank_bits - 1)
60 | HSDRAMC1_BF(CAS, info->cas)
61 | HSDRAMC1_BF(TWR, info->twr)
62 | HSDRAMC1_BF(TRC, info->trc)
63 | HSDRAMC1_BF(TRP, info->trp)
64 | HSDRAMC1_BF(TRCD, info->trcd)
65 | HSDRAMC1_BF(TRAS, info->tras)
66 | HSDRAMC1_BF(TXSR, info->txsr));
68 #ifdef CFG_SDRAM_16BIT
69 tmp |= HSDRAMC1_BIT(DBW);
70 sdram_size = 1 << (info->row_bits + info->col_bits
71 + info->bank_bits + 1);
73 sdram_size = 1 << (info->row_bits + info->col_bits
74 + info->bank_bits + 2);
77 hsdramc1_writel(&hsdramc, CR, tmp);
80 * Initialization sequence for SDRAM, from the data sheet:
82 * 1. A minimum pause of 200 us is provided to precede any
88 * 2. A Precharge All command is issued to the SDRAM
90 hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
91 hsdramc1_readl(&hsdramc, MR);
95 * 3. Eight auto-refresh (CBR) cycles are provided
97 hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_AUTO_REFRESH);
98 hsdramc1_readl(&hsdramc, MR);
99 for (i = 0; i < 8; i++)
103 * 4. A mode register set (MRS) cycle is issued to program
104 * SDRAM parameters, in particular CAS latency and burst
107 * CAS from info struct, burst length 1, serial burst type
109 hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_LOAD_MODE);
110 hsdramc1_readl(&hsdramc, MR);
111 writel(0, sdram + (info->cas << 4));
114 * 5. A Normal Mode command is provided, 3 clocks after tMRD
117 * From the timing diagram, it looks like tMRD is 3
118 * cycles...try a dummy read from the peripheral bus.
120 hsdramc1_readl(&hsdramc, MR);
121 hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_NORMAL);
122 hsdramc1_readl(&hsdramc, MR);
126 * 6. Write refresh rate into SDRAMC refresh timer count
127 * register (refresh rate = timing between refresh cycles).
129 * 15.6 us is a typical value for a burst of length one
131 hsdramc1_writel(&hsdramc, TR, (156 * (bus_hz / 1000)) / 10000);
133 printf("SDRAM: %u MB at address 0x%08lx\n",
134 sdram_size >> 20, info->phys_addr);
136 printf("Testing SDRAM...");
137 for (i = 0; i < sdram_size / 4; i++)
140 for (i = 0; i < sdram_size / 4; i++) {
143 printf("FAILED at address 0x%08lx\n",
144 info->phys_addr + i * 4);
145 printf("SDRAM: read 0x%lx, expected 0x%lx\n", tmp, i);
155 #endif /* CFG_HSDRAMC */