3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 #include <asm/arch/hardware.h>
38 /* read co-processor 15, register #1 (control register) */
39 static unsigned long read_p15_c1(void)
44 "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
48 /*printf("p15/c1 is = %08lx\n", value); */
52 /* write to co-processor 15, register #1 (control register) */
53 static void write_p15_c1(unsigned long value)
55 /*printf("write %08lx to p15/c1\n", value); */
57 "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
65 static void cp_delay(void)
69 /* copro seems to need some delay between reading and writing */
70 for (i=0; i<100; i++);
72 /* See also ARM Ref. Man. */
73 #define C1_MMU (1<<0) /* mmu off/on */
74 #define C1_ALIGN (1<<1) /* alignment faults off/on */
75 #define C1_IDC (1<<2) /* icache and/or dcache off/on */
76 #define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */
77 #define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
78 #define C1_SYS_PROT (1<<8) /* system protection */
79 #define C1_ROM_PROT (1<<9) /* ROM protection */
80 #define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
85 * setup up stack if necessary
88 IRQ_STACK_START = _armboot_end +
89 CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
90 FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
91 _armboot_real_end = FIQ_STACK_START + 4;
93 _armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
98 int cleanup_before_linux(void)
101 * this function is called just before we call linux
102 * it prepares the processor for linux
104 * we turn off caches etc ...
105 * and we set the CPU-speed to 73 MHz - see start.S for details
108 disable_interrupts();
112 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
115 #ifdef CFG_SOFT_RESET
116 extern void reset_cpu(ulong addr);
118 disable_interrupts();
121 AT91PS_USART us = AT91C_BASE_US1;
122 AT91PS_PIO pio = AT91C_BASE_PIOA;
124 /*shutdown the console to avoid strange chars during reset */
125 us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
127 /* Clear PA19 to trigger the hard reset */
128 pio->PIO_CODR = 0x00080000;
129 pio->PIO_OER = 0x00080000;
130 pio->PIO_PER = 0x00080000;
136 void icache_enable(void)
141 write_p15_c1(reg | C1_IDC);
144 void icache_disable(void)
149 write_p15_c1(reg & ~C1_IDC);
152 int icache_status(void)
154 return (read_p15_c1() & C1_IDC) != 0;
158 void dcache_enable(void)
163 write_p15_c1(reg | C1_IDC);
166 void dcache_disable(void)
171 write_p15_c1(reg & ~C1_IDC);
174 int dcache_status(void)
176 return (read_p15_c1() & C1_IDC) != 0;