3 #include <linux/config.h>
5 #include <asm/blackfin.h>
6 #include <asm/mem_init.h>
7 #include <asm/mach-common/bits/bootrom.h>
8 #include <asm/mach-common/bits/ebiu.h>
9 #include <asm/mach-common/bits/pll.h>
10 #include <asm/mach-common/bits/uart.h>
13 #if (CONFIG_CCLK_DIV == 1)
14 #define CONFIG_CCLK_ACT_DIV CCLK_DIV1
16 #if (CONFIG_CCLK_DIV == 2)
17 #define CONFIG_CCLK_ACT_DIV CCLK_DIV2
19 #if (CONFIG_CCLK_DIV == 4)
20 #define CONFIG_CCLK_ACT_DIV CCLK_DIV4
22 #if (CONFIG_CCLK_DIV == 8)
23 #define CONFIG_CCLK_ACT_DIV CCLK_DIV8
25 #ifndef CONFIG_CCLK_ACT_DIV
26 #define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
36 * PLL_LOCKCNT - how many SCLK Cycles to delay while PLL becomes stable
38 p0.h = hi(PLL_LOCKCNT);
39 p0.l = lo(PLL_LOCKCNT);
45 * Put SDRAM in self-refresh, incase anything is running
47 P2.H = hi(EBIU_SDGCTL);
48 P2.L = lo(EBIU_SDGCTL);
55 * Set PLL_CTL with the value that we calculate in R0
56 * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
57 * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
58 * - [7] = output delay (add 200ps of delay to mem signals)
59 * - [6] = input delay (add 200ps of input delay to mem signals)
60 * - [5] = PDWN : 1=All Clocks off
61 * - [3] = STOPCK : 1=Core Clock off
62 * - [1] = PLL_OFF : 1=Disable Power to PLL
63 * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
64 * all other bits set to zero
67 r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
68 r0 = r0 << 9; /* Shift it over, */
69 r1 = CONFIG_CLKIN_HALF; /* Do we need to divide CLKIN by 2? */
71 r1 = CONFIG_PLL_BYPASS; /* Bypass the PLL? */
72 r1 = r1 << 8; /* Shift it over */
73 r0 = r1 | r0; /* add them all together */
76 p0.l = lo(PLL_CTL); /* Load the address */
77 cli r2; /* Disable interrupts */
79 w[p0] = r0.l; /* Set the value */
80 idle; /* Wait for the PLL to stablize */
81 sti r2; /* Enable interrupts */
88 if ! CC jump check_again;
90 /* Configure SCLK & CCLK Dividers */
91 r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
98 * We now are running at speed, time to set the Async mem bank wait states
99 * This will speed up execution, since we are normally running from FLASH.
102 p2.h = (EBIU_AMBCTL1 >> 16);
103 p2.l = (EBIU_AMBCTL1 & 0xFFFF);
104 r0.h = (AMBCTL1VAL >> 16);
105 r0.l = (AMBCTL1VAL & 0xFFFF);
109 p2.h = (EBIU_AMBCTL0 >> 16);
110 p2.l = (EBIU_AMBCTL0 & 0xFFFF);
111 r0.h = (AMBCTL0VAL >> 16);
112 r0.l = (AMBCTL0VAL & 0xFFFF);
116 p2.h = (EBIU_AMGCTL >> 16);
117 p2.l = (EBIU_AMGCTL & 0xffff);
123 * Now, Initialize the SDRAM,
124 * start with the SDRAM Refresh Rate Control Register
126 p0.l = lo(EBIU_SDRRC);
127 p0.h = hi(EBIU_SDRRC);
133 * SDRAM Memory Bank Control Register - bank specific parameters
135 p0.l = (EBIU_SDBCTL & 0xFFFF);
136 p0.h = (EBIU_SDBCTL >> 16);
142 * SDRAM Global Control Register - global programmable parameters
143 * Disable self-refresh
145 P2.H = hi(EBIU_SDGCTL);
146 P2.L = lo(EBIU_SDGCTL);
151 * Check if SDRAM is already powered up, if it is, enable self-refresh
153 p0.h = hi(EBIU_SDSTAT);
154 p0.l = lo(EBIU_SDSTAT);
164 /* Write in the new value in the register */
165 R0.L = lo(mem_SDGCTL);
166 R0.H = hi(mem_SDGCTL);