git.sur5r.net Git - u-boot/blob - cpu/blackfin/cpu.c

   1 /*
   2  * U-boot - cpu.c CPU specific functions
   3  *
   4  * Copyright (c) 2005-2008 Analog Devices Inc.
   5  *
   6  * (C) Copyright 2000-2004
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * Licensed under the GPL-2 or later.
  10  */
  11
  12 #include <common.h>
  13 #include <command.h>
  14 #include <asm/blackfin.h>
  15 #include <asm/cplb.h>
  16 #include <asm/mach-common/bits/core.h>
  17 #include <asm/mach-common/bits/mpu.h>
  18 #include <asm/mach-common/bits/trace.h>
  19
  20 #include "cpu.h"
  21 #include "serial.h"
  22
  23 void icache_enable(void)
  24 {
  25         bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() | (IMC | ENICPLB));
  26         SSYNC();
  27 }
  28
  29 void icache_disable(void)
  30 {
  31         bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() & ~(IMC | ENICPLB));
  32         SSYNC();
  33 }
  34
  35 int icache_status(void)
  36 {
  37         return bfin_read_IMEM_CONTROL() & ENICPLB;
  38 }
  39
  40 void dcache_enable(void)
  41 {
  42         bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() | (ACACHE_BCACHE | ENDCPLB | PORT_PREF0));
  43         SSYNC();
  44 }
  45
  46 void dcache_disable(void)
  47 {
  48         bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() & ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0));
  49         SSYNC();
  50 }
  51
  52 int dcache_status(void)
  53 {
  54         return bfin_read_DMEM_CONTROL() & ENDCPLB;
  55 }
  56
  57 __attribute__ ((__noreturn__))
  58 void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
  59 {
  60         /* Build a NOP slide over the LDR jump block.  Whee! */
  61         serial_early_puts("NOP Slide\n");
  62         char nops[0xC];
  63         memset(nops, 0x00, sizeof(nops));
  64         extern char _stext_l1;
  65         memcpy(&_stext_l1 - sizeof(nops), nops, sizeof(nops));
  66
  67         if (!loaded_from_ldr) {
  68                 /* Relocate sections into L1 if the LDR didn't do it -- don't
  69                  * check length because the linker script does the size
  70                  * checking at build time.
  71                  */
  72                 serial_early_puts("L1 Relocate\n");
  73                 extern char _stext_l1, _etext_l1, _stext_l1_lma;
  74                 memcpy(&_stext_l1, &_stext_l1_lma, (&_etext_l1 - &_stext_l1));
  75                 extern char _sdata_l1, _edata_l1, _sdata_l1_lma;
  76                 memcpy(&_sdata_l1, &_sdata_l1_lma, (&_edata_l1 - &_sdata_l1));
  77         }
  78 #if defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
  79         /* The BF537 bootrom will reset the EBIU_AMGCTL register on us
  80          * after it has finished loading the LDR.  So configure it again.
  81          */
  82         else
  83                 bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
  84 #endif
  85
  86 #ifdef CONFIG_DEBUG_DUMP
  87         /* Turn on hardware trace buffer */
  88         bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
  89 #endif
  90
  91 #ifndef CONFIG_PANIC_HANG
  92         /* Reset upon a double exception rather than just hanging.
  93          * Do not do bfin_read on SWRST as that will reset status bits.
  94          */
  95         bfin_write_SWRST(DOUBLE_FAULT);
  96 #endif
  97
  98         serial_early_puts("Board init flash\n");
  99         board_init_f(bootflag);
 100 }
 101
 102 int exception_init(void)
 103 {
 104         bfin_write_EVT3(trap);
 105         return 0;
 106 }
 107
 108 int irq_init(void)
 109 {
 110 #ifdef SIC_IMASK0
 111         bfin_write_SIC_IMASK0(0);
 112         bfin_write_SIC_IMASK1(0);
 113 # ifdef SIC_IMASK2
 114         bfin_write_SIC_IMASK2(0);
 115 # endif
 116 #elif defined(SICA_IMASK0)
 117         bfin_write_SICA_IMASK0(0);
 118         bfin_write_SICA_IMASK1(0);
 119 #else
 120         bfin_write_SIC_IMASK(0);
 121 #endif
 122         bfin_write_EVT2(evt_default);   /* NMI */
 123         bfin_write_EVT5(evt_default);   /* hardware error */
 124         bfin_write_EVT6(evt_default);   /* core timer */
 125         bfin_write_EVT7(evt_default);
 126         bfin_write_EVT8(evt_default);
 127         bfin_write_EVT9(evt_default);
 128         bfin_write_EVT10(evt_default);
 129         bfin_write_EVT11(evt_default);
 130         bfin_write_EVT12(evt_default);
 131         bfin_write_EVT13(evt_default);
 132         bfin_write_EVT14(evt_default);
 133         bfin_write_EVT15(evt_default);
 134         bfin_write_ILAT(0);
 135         CSYNC();
 136         /* enable all interrupts except for core timer */
 137         irq_flags = 0xffffffbf;
 138         local_irq_enable();
 139         CSYNC();
 140         return 0;
 141 }