2 * initcode.c - Initialize the processor. This is usually entails things
3 * like external memory, voltage regulators, etc... Note that this file
4 * cannot make any function calls as it may be executed all by itself by
5 * the Blackfin's bootrom in LDR format.
7 * Copyright (c) 2004-2008 Analog Devices Inc.
9 * Licensed under the GPL-2 or later.
13 #include <asm/blackfin.h>
14 #include <asm/mach-common/bits/bootrom.h>
15 #include <asm/mach-common/bits/ebiu.h>
16 #include <asm/mach-common/bits/pll.h>
17 #include <asm/mach-common/bits/uart.h>
19 #define BFIN_IN_INITCODE
22 __attribute__((always_inline))
23 static inline uint32_t serial_init(void)
26 # ifdef BFIN_BOOT_UART_USE_RTS
27 # define BFIN_UART_USE_RTS 1
29 # define BFIN_UART_USE_RTS 0
31 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
34 /* force RTS rather than relying on auto RTS */
35 bfin_write_UART1_MCR(bfin_read_UART1_MCR() | FCPOL);
37 /* Wait for the line to clear up. We cannot rely on UART
38 * registers as none of them reflect the status of the RSR.
39 * Instead, we'll sleep for ~10 bit times at 9600 baud.
40 * We can precalc things here by assuming boot values for
41 * PLL rather than loading registers and calculating.
42 * baud = SCLK / (16 ^ (1 - EDBO) * Divisor)
44 * Divisor = (SCLK / baud) / 16
45 * SCLK = baud * 16 * Divisor
46 * SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5
47 * CCLK = (16 * Divisor * 5) * (9600 / 10)
48 * In reality, this will probably be just about 1 second delay,
49 * so assuming 9600 baud is OK (both as a very low and too high
50 * speed as this will buffer things enough).
52 #define _NUMBITS (10) /* how many bits to delay */
53 #define _LOWBAUD (9600) /* low baud rate */
54 #define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */
55 #define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */
56 #define _NUMINS (3) /* how many instructions in loop */
57 #define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
60 asm volatile("" : : : "memory");
65 if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
66 old_baud = serial_early_get_baud();
68 old_baud = CONFIG_BAUDRATE;
70 if (BFIN_DEBUG_EARLY_SERIAL) {
73 /* If the UART is off, that means we need to program
74 * the baud rate ourselves initially.
77 old_baud = CONFIG_BAUDRATE;
78 serial_early_set_baud(CONFIG_BAUDRATE);
85 __attribute__((always_inline))
86 static inline void serial_deinit(void)
89 if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
90 /* clear forced RTS rather than relying on auto RTS */
91 bfin_write_UART1_MCR(bfin_read_UART1_MCR() & ~FCPOL);
96 /* We need to reset the baud rate when we have early debug turned on
97 * or when we are booting over the UART.
98 * XXX: we should fix this to calc the old baud and restore it rather
99 * than hardcoding it via CONFIG_LDR_LOAD_BAUD ... but we have
100 * to figure out how to avoid the division in the baud calc ...
102 __attribute__((always_inline))
103 static inline void serial_reset_baud(uint32_t baud)
105 if (!BFIN_DEBUG_EARLY_SERIAL && CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
108 #ifndef CONFIG_LDR_LOAD_BAUD
109 # define CONFIG_LDR_LOAD_BAUD 115200
112 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
113 serial_early_set_baud(baud);
114 else if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
115 serial_early_set_baud(CONFIG_LDR_LOAD_BAUD);
117 serial_early_set_baud(CONFIG_BAUDRATE);
120 __attribute__((always_inline))
121 static inline void serial_putc(char c)
123 if (!BFIN_DEBUG_EARLY_SERIAL)
131 while (!(*pUART_LSR & TEMT))
136 /* Max SCLK can be 133MHz ... dividing that by 4 gives
137 * us a freq of 33MHz for SPI which should generally be
138 * slow enough for the slow reads the bootrom uses.
140 #ifndef CONFIG_SPI_BAUD_INITBLOCK
141 # define CONFIG_SPI_BAUD_INITBLOCK 4
144 /* PLL_DIV defines */
145 #ifndef CONFIG_PLL_DIV_VAL
146 # if (CONFIG_CCLK_DIV == 1)
147 # define CONFIG_CCLK_ACT_DIV CCLK_DIV1
148 # elif (CONFIG_CCLK_DIV == 2)
149 # define CONFIG_CCLK_ACT_DIV CCLK_DIV2
150 # elif (CONFIG_CCLK_DIV == 4)
151 # define CONFIG_CCLK_ACT_DIV CCLK_DIV4
152 # elif (CONFIG_CCLK_DIV == 8)
153 # define CONFIG_CCLK_ACT_DIV CCLK_DIV8
155 # define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
157 # define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
160 #ifndef CONFIG_PLL_LOCKCNT_VAL
161 # define CONFIG_PLL_LOCKCNT_VAL 0x0300
164 #ifndef CONFIG_PLL_CTL_VAL
165 # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
168 #ifndef CONFIG_EBIU_RSTCTL_VAL
169 # define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
172 #ifndef CONFIG_EBIU_MBSCTL_VAL
173 # define CONFIG_EBIU_MBSCTL_VAL 0
176 /* Make sure our voltage value is sane so we don't blow up! */
177 #ifndef CONFIG_VR_CTL_VAL
178 # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
179 # if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
180 # define CCLK_VLEV_120 400000000
181 # define CCLK_VLEV_125 533000000
182 # elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
183 # define CCLK_VLEV_120 401000000
184 # define CCLK_VLEV_125 401000000
185 # elif defined(__ADSPBF561__)
186 # define CCLK_VLEV_120 300000000
187 # define CCLK_VLEV_125 501000000
189 # if BFIN_CCLK < CCLK_VLEV_120
190 # define CONFIG_VR_CTL_VLEV VLEV_120
191 # elif BFIN_CCLK < CCLK_VLEV_125
192 # define CONFIG_VR_CTL_VLEV VLEV_125
194 # define CONFIG_VR_CTL_VLEV VLEV_130
196 # if defined(__ADSPBF52x__) /* TBD; use default */
197 # undef CONFIG_VR_CTL_VLEV
198 # define CONFIG_VR_CTL_VLEV VLEV_110
199 # elif defined(__ADSPBF54x__) /* TBD; use default */
200 # undef CONFIG_VR_CTL_VLEV
201 # define CONFIG_VR_CTL_VLEV VLEV_120
202 # elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
203 # undef CONFIG_VR_CTL_VLEV
204 # define CONFIG_VR_CTL_VLEV VLEV_125
207 # ifdef CONFIG_BFIN_MAC
208 # define CONFIG_VR_CTL_CLKBUF CLKBUFOE
210 # define CONFIG_VR_CTL_CLKBUF 0
213 # if defined(__ADSPBF52x__)
214 # define CONFIG_VR_CTL_FREQ FREQ_1000
216 # define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
219 # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
222 BOOTROM_CALLED_FUNC_ATTR
223 void initcode(ADI_BOOT_DATA *bootstruct)
225 uint32_t old_baud = serial_init();
227 #ifdef CONFIG_HW_WATCHDOG
228 # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
229 # define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
231 /* Program the watchdog with an initial timeout of ~20 seconds.
232 * Hopefully that should be long enough to load the u-boot LDR
233 * (from wherever) and then the common u-boot code can take over.
234 * In bypass mode, the start.S would have already set a much lower
235 * timeout, so don't clobber that.
237 if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
238 bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
239 bfin_write_WDOG_CTL(0);
245 /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
246 * fast read, so we need to slow down the SPI clock a lot more during
247 * boot. Once we switch over to u-boot's SPI flash driver, we'll
248 * increase the speed appropriately.
250 if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
252 bfin_write_SPI0_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
254 bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
259 /* Disable all peripheral wakeups except for the PLL event. */
261 bfin_write_SIC_IWR0(1);
262 bfin_write_SIC_IWR1(0);
264 bfin_write_SIC_IWR2(0);
266 #elif defined(SICA_IWR0)
267 bfin_write_SICA_IWR0(1);
268 bfin_write_SICA_IWR1(0);
270 bfin_write_SIC_IWR(1);
273 /* With newer bootroms, we use the helper function to set up
274 * the memory controller. Older bootroms lacks such helpers
275 * so we do it ourselves.
277 if (BOOTROM_CAPS_SYSCONTROL) {
280 ADI_SYSCTRL_VALUES memory_settings;
281 memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
282 memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
283 memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
284 memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
285 syscontrol(SYSCTRL_WRITE | SYSCTRL_VRCTL | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT |
286 (CONFIG_VR_CTL_VAL & FREQ_MASK ? SYSCTRL_INTVOLTAGE : SYSCTRL_EXTVOLTAGE), &memory_settings, NULL);
290 bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
294 /* Only reprogram when needed to avoid triggering unnecessary
295 * PLL relock sequences.
297 if (bfin_read_VR_CTL() != CONFIG_VR_CTL_VAL) {
299 bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
305 bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
309 /* Only reprogram when needed to avoid triggering unnecessary
310 * PLL relock sequences.
312 if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
314 bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
319 /* Since we've changed the SCLK above, we may need to update
320 * the UART divisors (UART baud rates are based on SCLK).
322 serial_reset_baud(old_baud);
326 /* Program the async banks controller. */
327 bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
328 bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
329 bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
332 /* Not all parts have these additional MMRs. */
333 bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
334 bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
335 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
340 /* Program the external memory controller. */
342 bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
343 bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
344 bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
345 bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
346 # ifdef CONFIG_EBIU_DDRCTL3_VAL
347 /* default is disable, so don't need to force this */
348 bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
351 bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
352 bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
353 bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
358 /* Restore all peripheral wakeups. */
360 bfin_write_SIC_IWR0(-1);
361 bfin_write_SIC_IWR1(-1);
363 bfin_write_SIC_IWR2(-1);
365 #elif defined(SICA_IWR0)
366 bfin_write_SICA_IWR0(-1);
367 bfin_write_SICA_IWR1(-1);
369 bfin_write_SIC_IWR(-1);