3 * (C) Copyright 2004 eslab.whut.edu.cn
4 * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
33 #include <asm/arch/ixp425.h>
34 #include <asm/arch/ixp425pci.h>
36 static void non_prefetch_read (unsigned int addr, unsigned int cmd,
38 static void non_prefetch_write (unsigned int addr, unsigned int cmd,
40 static void configure_pins (void);
41 static void sys_pci_gpio_clock_config (void);
42 static void pci_bus_scan (void);
43 static int pci_device_exists (unsigned int deviceNo);
44 static void sys_pci_bar_info_get (unsigned int devnum, unsigned int bus,
45 unsigned int dev, unsigned int func);
46 static void sys_pci_device_bars_write (void);
47 static void calc_bars (PciBar * Bars[], unsigned int nBars,
48 unsigned int startAddr);
50 #define PCI_MEMORY_BUS 0x00000000
51 #define PCI_MEMORY_PHY 0x48000000
52 #define PCI_MEMORY_SIZE 0x04000000
54 #define PCI_MEM_BUS 0x40000000
55 #define PCI_MEM_PHY 0x00000000
56 #define PCI_MEM_SIZE 0x04000000
58 #define PCI_IO_BUS 0x40000000
59 #define PCI_IO_PHY 0x50000000
60 #define PCI_IO_SIZE 0x10000000
62 struct pci_controller hose;
64 unsigned int nDevices;
67 PciBar *memBars[IXP425_PCI_MAX_BAR];
68 PciBar *ioBars[IXP425_PCI_MAX_BAR];
69 PciDevice devices[IXP425_PCI_MAX_FUNC_ON_BUS];
71 void out_8 (volatile unsigned *addr, char val)
76 void out_le16 (volatile unsigned *addr, unsigned short val)
78 *addr = cpu_to_le16 (val);
81 void out_le32 (volatile unsigned *addr, unsigned int val)
83 *addr = cpu_to_le32 (val);
86 unsigned char in_8 (volatile unsigned *addr)
94 unsigned short in_le16 (volatile unsigned *addr)
99 val = le16_to_cpu (val);
103 unsigned in_le32 (volatile unsigned *addr)
108 val = le32_to_cpu (val);
112 int pci_read_config_dword (pci_dev_t dev, int where, unsigned int *val)
117 /*address bits 31:28 specify the device 10:8 specify the function */
118 /*Set the address to be read */
119 addr = BIT ((31 - dev)) | (where & ~3);
120 non_prefetch_read (addr, NP_CMD_CONFIGREAD, &retval);
127 int pci_read_config_word (pci_dev_t dev, int where, unsigned short *val)
132 unsigned int byteEnables;
135 /*byte enables are 4 bits active low, the position of each
136 bit maps to the byte that it enables */
138 (~(BIT (n) | BIT ((n + 1)))) &
139 IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
140 byteEnables = byteEnables << PCI_NP_CBE_BESL;
141 /*address bits 31:28 specify the device 10:8 specify the function */
142 /*Set the address to be read */
143 addr = BIT ((31 - dev)) | (where & ~3);
144 non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
146 /*Pick out the word we are interested in */
147 *val = (retval >> (8 * n));
152 int pci_read_config_byte (pci_dev_t dev, int where, unsigned char *val)
156 unsigned int byteEnables;
160 /*byte enables are 4 bits, active low, the position of each
161 bit maps to the byte that it enables */
162 byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
163 byteEnables = byteEnables << PCI_NP_CBE_BESL;
165 /*address bits 31:28 specify the device, 10:8 specify the function */
166 /*Set the address to be read */
167 addr = BIT ((31 - dev)) | (where & ~3);
168 non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
169 /*Pick out the byte we are interested in */
170 *val = (retval >> (8 * n));
175 int pci_write_config_byte (pci_dev_t dev, int where, unsigned char val)
178 unsigned int byteEnables;
183 /*byte enables are 4 bits active low, the position of each
184 bit maps to the byte that it enables */
185 byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
186 byteEnables = byteEnables << PCI_NP_CBE_BESL;
187 ldata = val << (8 * n);
188 /*address bits 31:28 specify the device 10:8 specify the function */
189 /*Set the address to be written */
190 addr = BIT ((31 - dev)) | (where & ~3);
191 non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
196 int pci_write_config_word (pci_dev_t dev, int where, unsigned short val)
199 unsigned int byteEnables;
204 /*byte enables are 4 bits active low, the position of each
205 bit maps to the byte that it enables */
207 (~(BIT (n) | BIT ((n + 1)))) &
208 IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
209 byteEnables = byteEnables << PCI_NP_CBE_BESL;
210 ldata = val << (8 * n);
211 /*address bits 31:28 specify the device 10:8 specify the function */
212 /*Set the address to be written */
213 addr = BIT (31 - dev) | (where & ~3);
214 non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
219 int pci_write_config_dword (pci_dev_t dev, int where, unsigned int val)
223 /*address bits 31:28 specify the device 10:8 specify the function */
224 /*Set the address to be written */
225 addr = BIT (31 - dev) | (where & ~3);
226 non_prefetch_write (addr, NP_CMD_CONFIGWRITE, val);
231 void non_prefetch_read (unsigned int addr,
232 unsigned int cmd, unsigned int *data)
234 REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr);
236 /*set up and execute the read */
237 REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd);
239 /*The result of the read is now in np_rdata */
240 REG_READ (PCI_CSR_BASE, PCI_NP_RDATA_OFFSET, *data);
245 void non_prefetch_write (unsigned int addr,
246 unsigned int cmd, unsigned int data)
249 REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr);
250 /*set up the write */
251 REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd);
252 /*Execute the write by writing to NP_WDATA */
253 REG_WRITE (PCI_CSR_BASE, PCI_NP_WDATA_OFFSET, data);
259 * PCI controller config registers are accessed through these functions
260 * i.e. these allow us to set up our own BARs etc.
262 void crp_read (unsigned int offset, unsigned int *data)
264 REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, offset);
265 REG_READ (PCI_CSR_BASE, PCI_CRP_RDATA_OFFSET, *data);
268 void crp_write (unsigned int offset, unsigned int data)
270 /*The CRP address register bit 16 indicates that we want to do a write */
271 REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET,
272 PCI_CRP_WRITE | offset);
273 REG_WRITE (PCI_CSR_BASE, PCI_CRP_WDATA_OFFSET, data);
276 /*struct pci_controller *hose*/
277 void pci_ixp_init (struct pci_controller *hose)
281 hose->first_busno = 0;
282 hose->last_busno = 0x00;
284 /* System memory space */
285 pci_set_region (hose->regions + 0,
287 PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_MEMORY);
289 /* PCI memory space */
290 pci_set_region (hose->regions + 1,
292 PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM);
294 pci_set_region (hose->regions + 2,
295 PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO);
297 hose->region_count = 3;
299 pci_register_hose (hose);
302 ==========================================================
304 ==========================================================
306 REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
308 REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
312 READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval);
313 WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval & (~(1 << 13)));
315 sys_pci_gpio_clock_config ();
316 REG_WRITE (PCI_CSR_BASE, PCI_INTEN_OFFSET, 0);
318 READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval);
319 WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval | (1 << 13));
321 crp_write (PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_0_DEFAULT);
322 crp_write (PCI_CFG_BASE_ADDRESS_1, IXP425_PCI_BAR_1_DEFAULT);
323 crp_write (PCI_CFG_BASE_ADDRESS_2, IXP425_PCI_BAR_2_DEFAULT);
324 crp_write (PCI_CFG_BASE_ADDRESS_3, IXP425_PCI_BAR_3_DEFAULT);
325 crp_write (PCI_CFG_BASE_ADDRESS_4, IXP425_PCI_BAR_4_DEFAULT);
326 crp_write (PCI_CFG_BASE_ADDRESS_5, IXP425_PCI_BAR_5_DEFAULT);
327 /*Setup PCI-AHB and AHB-PCI address mappings */
328 REG_WRITE (PCI_CSR_BASE, PCI_AHBMEMBASE_OFFSET,
329 IXP425_PCI_AHBMEMBASE_DEFAULT);
331 REG_WRITE (PCI_CSR_BASE, PCI_AHBIOBASE_OFFSET,
332 IXP425_PCI_AHBIOBASE_DEFAULT);
334 REG_WRITE (PCI_CSR_BASE, PCI_PCIMEMBASE_OFFSET,
335 IXP425_PCI_PCIMEMBASE_DEFAULT);
337 crp_write (PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM);
339 REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
340 regval |= PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS;
341 REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
342 crp_write (PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME);
345 pci_write_config_word (0, PCI_CFG_COMMAND, INITIAL_PCI_CMD);
346 REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
347 | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE);
348 #ifdef CONFIG_PCI_SCAN_SHOW
349 printf ("Device bus dev func deviceID vendorID \n");
354 void configure_pins (void)
358 /* Disable clock on GPIO PIN 14 */
359 READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
360 WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval & (~(1 << 8)));
361 READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
363 READ_GPIO_REG (IXP425_GPIO_GPOER, regval);
364 WRITE_GPIO_REG (IXP425_GPIO_GPOER,
365 (((~(3 << 13)) & regval) | (0xf << 8)));
366 READ_GPIO_REG (IXP425_GPIO_GPOER, regval);
368 READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval);
369 WRITE_GPIO_REG (IXP425_GPIO_GPIT2R,
371 ((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1)));
372 READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval);
374 READ_GPIO_REG (IXP425_GPIO_GPISR, regval);
375 WRITE_GPIO_REG (IXP425_GPIO_GPISR, (regval | (0xf << 8)));
376 READ_GPIO_REG (IXP425_GPIO_GPISR, regval);
379 void sys_pci_gpio_clock_config (void)
383 READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
385 WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
386 READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
388 WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
391 void pci_bus_scan (void)
393 unsigned int bus = 0, dev, func = 0;
394 unsigned short data16;
396 unsigned char intPin;
398 /* Assign first device to ourselves */
400 devices[0].device = 0;
403 crp_read (PCI_CFG_VENDOR_ID, &data32);
405 devices[0].vendor_id = data32 & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK;
406 devices[0].device_id = data32 >> 16;
407 devices[0].error = FALSE;
408 devices[0].bar[NO_BAR].size = 0; /*dummy - required */
415 for (dev = 0; dev < IXP425_PCI_MAX_DEV; dev++) {
417 /*Check whether a device is present */
418 if (pci_device_exists (dev) != TRUE) {
420 /*Clear error bits in ISR, write 1 to clear */
421 REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
422 | PCI_ISR_PFE | PCI_ISR_PPE |
427 /*A device is present, add an entry to the array */
428 devices[nDevices].bus = bus;
429 devices[nDevices].device = dev;
430 devices[nDevices].func = func;
432 pci_read_config_word (dev, PCI_CFG_VENDOR_ID, &data16);
434 devices[nDevices].vendor_id = data16;
436 pci_read_config_word (dev, PCI_CFG_DEVICE_ID, &data16);
437 devices[nDevices].device_id = data16;
439 /*The device is functioning correctly, set error to FALSE */
440 devices[nDevices].error = FALSE;
442 /*Figure out what BARs are on this device */
443 sys_pci_bar_info_get (nDevices, bus, dev, func);
444 /*Figure out what INTX# line the card uses */
445 pci_read_config_byte (dev, PCI_CFG_DEV_INT_PIN, &intPin);
447 /*assign the appropriate irq line */
448 if (intPin > PCI_IRQ_LINES) {
449 devices[nDevices].error = TRUE;
450 } else if (intPin != 0) {
451 /*This device uses an interrupt line */
452 /*devices[nDevices].irq = ixp425PciIntTranslate[dev][intPin-1]; */
453 devices[nDevices].irq = intPin;
455 #ifdef CONFIG_PCI_SCAN_SHOW
456 printf ("%06d %03d %03d %04d %08d %08x\n", nDevices,
457 devices[nDevices].vendor_id);
463 calc_bars (memBars, nMBars, IXP425_PCI_BAR_MEM_BASE);
464 sys_pci_device_bars_write ();
466 REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
467 | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE);
470 void sys_pci_bar_info_get (unsigned int devnum,
472 unsigned int dev, unsigned int func)
478 pci_write_config_dword (devnum,
479 PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_QUERY);
480 pci_read_config_dword (devnum, PCI_CFG_BASE_ADDRESS_0, &data32);
482 devices[devnum].bar[0].address = (data32 & 1);
488 devices[devnum].bar[0].size = size;
490 if (nIOBars < IXP425_PCI_MAX_BAR) {
491 ioBars[nIOBars++] = &devices[devnum].bar[0];
495 tmp = data32 & ~IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
497 devices[devnum].bar[0].size = size;
499 if (nMBars < IXP425_PCI_MAX_BAR) {
500 memBars[nMBars++] = &devices[devnum].bar[0];
502 devices[devnum].error = TRUE;
507 devices[devnum].bar[1].size = 0;
510 void sortBars (PciBar * Bars[], unsigned int nBars)
519 /* Sort biggest to smallest */
520 for (i = 0; i < nBars - 1; i++) {
521 for (j = i + 1; j < nBars; j++) {
522 if (Bars[j]->size > Bars[i]->size) {
532 void calc_bars (PciBar * Bars[], unsigned int nBars, unsigned int startAddr)
540 for (i = 0; i < nBars; i++) {
541 Bars[i]->address |= startAddr;
542 startAddr += Bars[i]->size;
546 void sys_pci_device_bars_write (void)
551 for (i = 1; i < nDevices; i++) {
552 if (devices[i].error) {
556 pci_write_config_dword (devices[i].device,
557 PCI_CFG_BASE_ADDRESS_0,
558 devices[i].bar[0].address);
559 addr = (BIT (31 - devices[i].device) |
560 (0 << PCI_NP_AD_FUNCSL) |
561 (PCI_CFG_BASE_ADDRESS_0) ) & ~3;
562 pci_write_config_dword (devices[i].device,
563 PCI_CFG_DEV_INT_LINE, devices[i].irq);
565 pci_write_config_word (devices[i].device,
566 PCI_CFG_COMMAND, INITIAL_PCI_CMD);
572 int pci_device_exists (unsigned int deviceNo)
574 unsigned int vendorId;
577 pci_read_config_dword (deviceNo, PCI_CFG_VENDOR_ID, &vendorId);
579 /* There are two ways to find out an empty device.
580 * 1. check Master Abort bit after the access.
581 * 2. check whether the vendor id read back is 0x0.
583 REG_READ (PCI_CSR_BASE, PCI_ISR_OFFSET, regval);
584 if ((vendorId != 0x0) && ((regval & PCI_ISR_PFE) == 0)) {
587 /*no device present, make sure that the master abort bit is reset */
589 REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PFE);
593 pci_dev_t pci_find_devices (struct pci_device_id * ids, int devNo)
596 unsigned int devdidvid;
598 unsigned int vendorId, deviceId;
600 vendorId = ids->vendor;
601 deviceId = ids->device;
602 didvid = ((deviceId << 16) & IXP425_PCI_TOP_WORD_OF_LONG_MASK) |
603 (vendorId & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK);
605 for (i = devNo + 1; i < nDevices; i++) {
607 pci_read_config_dword (devices[i].device, PCI_CFG_VENDOR_ID,
610 if (devdidvid == didvid) {
611 return devices[i].device;
616 #endif /* CONFIG_PCI */