3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * (C) Copyright 2007 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/immap.h>
34 * Breath some life into the CPU...
36 * Set up the memory map,
37 * initialize a bunch of registers,
38 * initialize the UPM's
42 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
43 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
44 volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
45 volatile scm_t *scm = (scm_t *) MMAP_SCM;
47 /* watchdog is enabled by default - disable the watchdog */
48 #ifndef CONFIG_WATCHDOG
52 scm->rambar = (CFG_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
54 /* Port configuration */
57 #if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
58 fbcs->csar0 = CFG_CS0_BASE;
59 fbcs->cscr0 = CFG_CS0_CTRL;
60 fbcs->csmr0 = CFG_CS0_MASK;
63 #if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
64 gpio->par_cs |= GPIO_PAR_CS_CS1;
65 fbcs->csar1 = CFG_CS1_BASE;
66 fbcs->cscr1 = CFG_CS1_CTRL;
67 fbcs->csmr1 = CFG_CS1_MASK;
70 #if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
71 gpio->par_cs |= GPIO_PAR_CS_CS2;
72 fbcs->csar2 = CFG_CS2_BASE;
73 fbcs->cscr2 = CFG_CS2_CTRL;
74 fbcs->csmr2 = CFG_CS2_MASK;
77 #if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
78 gpio->par_cs |= GPIO_PAR_CS_CS3;
79 fbcs->csar3 = CFG_CS3_BASE;
80 fbcs->cscr3 = CFG_CS3_CTRL;
81 fbcs->csmr3 = CFG_CS3_MASK;
84 #if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
85 gpio->par_cs |= GPIO_PAR_CS_CS4;
86 fbcs->csar4 = CFG_CS4_BASE;
87 fbcs->cscr4 = CFG_CS4_CTRL;
88 fbcs->csmr4 = CFG_CS4_MASK;
91 #if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
92 gpio->par_cs |= GPIO_PAR_CS_CS5;
93 fbcs->csar5 = CFG_CS5_BASE;
94 fbcs->cscr5 = CFG_CS5_CTRL;
95 fbcs->csmr5 = CFG_CS5_MASK;
98 #if (defined(CFG_CS6_BASE) && defined(CFG_CS6_MASK) && defined(CFG_CS6_CTRL))
99 gpio->par_cs |= GPIO_PAR_CS_CS6;
100 fbcs->csar6 = CFG_CS6_BASE;
101 fbcs->cscr6 = CFG_CS6_CTRL;
102 fbcs->csmr6 = CFG_CS6_MASK;
105 #if (defined(CFG_CS7_BASE) && defined(CFG_CS7_MASK) && defined(CFG_CS7_CTRL))
106 gpio->par_cs |= GPIO_PAR_CS_CS7;
107 fbcs->csar7 = CFG_CS7_BASE;
108 fbcs->cscr7 = CFG_CS7_CTRL;
109 fbcs->csmr7 = CFG_CS7_MASK;
112 #ifdef CONFIG_FSL_I2C
113 gpio->par_feci2c &= ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK);
114 gpio->par_feci2c |= (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA);
121 * initialize higher level parts of CPU like timers
128 void uart_port_conf(void)
130 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
133 switch (CFG_UART_PORT) {
135 gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
139 (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
142 gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);