2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/m5272.h>
30 #include <asm/immap_5272.h>
34 #include <asm/m5282.h>
35 #include <asm/immap_5282.h>
42 #define FEC_ADDR (CFG_MBAR + 0x840)
45 #define FEC_ADDR (CFG_MBAR + 0x1000)
51 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
53 #ifdef CFG_DISCOVER_PHY
55 static void mii_discover_phy (void);
58 /* Ethernet Transmit and Receive Buffers */
59 #define DBUF_LENGTH 1520
65 #define PKT_MAXBUF_SIZE 1518
66 #define PKT_MINBUF_SIZE 64
67 #define PKT_MAXBLR_SIZE 1520
70 static char txbuf[DBUF_LENGTH];
72 static uint rxIdx; /* index of the current RX buffer */
73 static uint txIdx; /* index of the current TX buffer */
76 * FEC Ethernet Tx and Rx buffer descriptors allocated at the
77 * immr->udata_bd address on Dual-Port RAM
78 * Provide for Double Buffering
81 typedef volatile struct CommonBufferDescriptor {
82 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
83 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
86 static RTXBD *rtx = NULL;
88 int eth_send (volatile void *packet, int length)
91 volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
97 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
102 if (j >= TOUT_LOOP) {
103 printf ("TX not ready\n");
106 rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
107 rtx->txbd[txIdx].cbd_datlen = length;
108 rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
110 /* Activate transmit Buffer Descriptor polling */
111 fecp->fec_x_des_active = 0x01000000; /* Descriptor polling active */
114 while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
115 && (j < TOUT_LOOP)) {
119 if (j >= TOUT_LOOP) {
120 printf ("TX timeout\n");
123 printf ("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
124 __FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc,
125 (rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2);
128 /* return only status bits */ ;
129 rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
131 txIdx = (txIdx + 1) % TX_BUF_CNT;
139 volatile fec_t *fecp = (fec_t *) FEC_ADDR;
142 /* section 16.9.23.2 */
143 if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
145 break; /* nothing received - leave for() loop */
148 length = rtx->rxbd[rxIdx].cbd_datlen;
150 if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
152 printf ("%s[%d] err: %x\n",
153 __FUNCTION__, __LINE__,
154 rtx->rxbd[rxIdx].cbd_sc);
157 /* Pass the packet up to the protocol layers. */
158 NetReceive (NetRxPackets[rxIdx], length - 4);
161 /* Give the buffer back to the FEC. */
162 rtx->rxbd[rxIdx].cbd_datlen = 0;
164 /* wrap around buffer index when necessary */
165 if ((rxIdx + 1) >= PKTBUFSRX) {
166 rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
167 (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
170 rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
174 /* Try to fill Buffer Descriptors */
175 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
181 /**************************************************************
183 * FEC Ethernet Initialization Routine
185 *************************************************************/
186 #define FEC_ECNTRL_ETHER_EN 0x00000002
187 #define FEC_ECNTRL_RESET 0x00000001
189 #define FEC_RCNTRL_BC_REJ 0x00000010
190 #define FEC_RCNTRL_PROM 0x00000008
191 #define FEC_RCNTRL_MII_MODE 0x00000004
192 #define FEC_RCNTRL_DRT 0x00000002
193 #define FEC_RCNTRL_LOOP 0x00000001
195 #define FEC_TCNTRL_FDEN 0x00000004
196 #define FEC_TCNTRL_HBC 0x00000002
197 #define FEC_TCNTRL_GTS 0x00000001
199 #define FEC_RESET_DELAY 50000
201 int eth_init (bd_t * bd)
205 volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
208 * A delay is required between a reset of the FEC block and
209 * initialization of other FEC registers because the reset takes
210 * some time to complete. If you don't delay, subsequent writes
211 * to FEC registers might get killed by the reset routine which is
214 fecp->fec_ecntrl = FEC_ECNTRL_RESET;
216 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
220 if (i == FEC_RESET_DELAY) {
221 printf ("FEC_RESET_DELAY timeout\n");
225 /* We use strictly polling mode only
229 /* Clear any pending interrupt */
230 fecp->fec_ievent = 0xffffffff;
232 /* Set station address */
233 #define ea bd->bi_enetaddr
234 fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) |
235 (ea[2] << 8) | (ea[3]);
236 fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16);
238 printf ("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n",
239 ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]);
243 /* Clear multicast address hash table
245 fecp->fec_hash_table_high = 0;
246 fecp->fec_hash_table_low = 0;
248 /* Set maximum receive buffer size.
250 fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
253 * Setup Buffers and Buffer Desriptors
259 rtx = (RTXBD *) CFG_ENET_BD_BASE;
263 * Setup Receiver Buffer Descriptors (13.14.24.18)
267 for (i = 0; i < PKTBUFSRX; i++) {
268 rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
269 rtx->rxbd[i].cbd_datlen = 0; /* Reset */
270 rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
272 rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
275 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
279 for (i = 0; i < TX_BUF_CNT; i++) {
280 rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
281 rtx->txbd[i].cbd_datlen = 0; /* Reset */
282 rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
284 rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
286 /* Set receive and transmit descriptor base
288 fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
289 fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
293 #if 0 /* Full duplex mode */
294 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE;
295 fecp->fec_x_cntrl = FEC_TCNTRL_FDEN;
296 #else /* Half duplex mode */
297 fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT;
298 fecp->fec_x_cntrl = 0;
301 fecp->fec_mii_speed = 0x0e;
303 /* Configure port B for MII.
305 /* port initialization was already made in cpu_init_f() */
307 /* Now enable the transmit and receive processing
309 fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
311 #ifdef CFG_DISCOVER_PHY
312 /* wait for the PHY to wake up after reset */
316 /* And last, try to fill Rx Buffer Descriptors */
317 fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
324 volatile fec_t *fecp = (fec_t *) FEC_ADDR;
326 fecp->fec_ecntrl = 0;
330 #if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
332 static int phyaddr = -1; /* didn't find a PHY yet */
335 /* Make MII read/write commands for the FEC.
338 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \
341 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \
342 (REG & 0x1f) << 18) | \
345 /* Interrupt events/masks.
347 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
348 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
349 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
350 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
351 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
352 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
353 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
354 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
355 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
356 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
358 /* PHY identification
360 #define PHY_ID_LXT970 0x78100000 /* LXT970 */
361 #define PHY_ID_LXT971 0x001378e0 /* LXT971 and 972 */
362 #define PHY_ID_82555 0x02a80150 /* Intel 82555 */
363 #define PHY_ID_QS6612 0x01814400 /* QS6612 */
364 #define PHY_ID_AMD79C784 0x00225610 /* AMD 79C784 */
365 #define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
366 #define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
368 /* send command to phy using mii, wait for result */
369 static uint mii_send (uint mii_cmd)
372 volatile fec_t *ep = (fec_t *) (FEC_ADDR);
374 ep->fec_mii_data = mii_cmd; /* command to phy */
376 /* wait for mii complete */
377 while (!(ep->fec_ievent & FEC_ENET_MII)); /* spin until done */
378 mii_reply = ep->fec_mii_data; /* result from phy */
379 ep->fec_ievent = FEC_ENET_MII; /* clear MII complete */
381 printf ("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n",
382 __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply);
384 return (mii_reply & 0xffff); /* data read from phy */
386 #endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CFG_CMD_MII) */
388 #if defined(CFG_DISCOVER_PHY)
389 static void mii_discover_phy (void)
391 #define MAX_PHY_PASSES 11
395 phyaddr = -1; /* didn't find a PHY yet */
396 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) {
398 /* PHY may need more time to recover from reset.
399 * The LXT970 needs 50ms typical, no maximum is
400 * specified, so wait 10ms before try again.
401 * With 11 passes this gives it 100ms to wake up.
403 udelay (10000); /* wait 10ms */
405 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) {
406 phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1));
408 printf ("PHY type 0x%x pass %d type ", phytype, pass);
410 if (phytype != 0xffff) {
413 phytype |= mii_send (mk_mii_read (phyno,
417 printf ("PHY @ 0x%x pass %d type ", phyno,
419 switch (phytype & 0xfffffff0) {
432 case PHY_ID_AMD79C784:
433 printf ("AMD79C784\n");
435 case PHY_ID_LSI80225B:
436 printf ("LSI L80225/B\n");
439 printf ("0x%08x\n", phytype);
447 printf ("No PHY device found.\n");
450 #endif /* CFG_DISCOVER_PHY */
452 #if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
454 static int mii_init_done = 0;
456 /****************************************************************************
457 * mii_init -- Initialize the MII for MII command without ethernet
458 * This function is a subset of eth_init
459 ****************************************************************************
463 volatile fec_t *fecp = (fec_t *) (FEC_ADDR);
467 if (mii_init_done != 0) {
472 * A delay is required between a reset of the FEC block and
473 * initialization of other FEC registers because the reset takes
474 * some time to complete. If you don't delay, subsequent writes
475 * to FEC registers might get killed by the reset routine which is
479 fecp->fec_ecntrl = FEC_ECNTRL_RESET;
481 (fecp->fec_ecntrl & FEC_ECNTRL_RESET) && (i < FEC_RESET_DELAY);
485 if (i == FEC_RESET_DELAY) {
486 printf ("FEC_RESET_DELAY timeout\n");
490 /* We use strictly polling mode only
494 /* Clear any pending interrupt
496 fecp->fec_ievent = 0xffffffff;
499 fecp->fec_mii_speed = 0x0e;
501 /* Configure port B for MII.
503 /* port initialization was already made in cpu_init_f() */
505 /* Now enable the transmit and receive processing */
506 fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
511 /*****************************************************************************
512 * Read and write a MII PHY register, routines used by MII Utilities
514 * FIXME: These routines are expected to return 0 on success, but mii_send
515 * does _not_ return an error code. Maybe 0xFFFF means error, i.e.
516 * no PHY connected...
517 * For now always return 0.
518 * FIXME: These routines only work after calling eth_init() at least once!
519 * Otherwise they hang in mii_send() !!! Sorry!
520 *****************************************************************************/
522 int mcf52x2_miiphy_read (char *devname, unsigned char addr,
523 unsigned char reg, unsigned short *value)
525 short rdreg; /* register working value */
528 printf ("miiphy_read(0x%x) @ 0x%x = ", reg, addr);
530 rdreg = mii_send (mk_mii_read (addr, reg));
535 printf ("0x%04x\n", *value);
541 int mcf52x2_miiphy_write (char *devname, unsigned char addr,
542 unsigned char reg, unsigned short value)
544 short rdreg; /* register working value */
547 printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
550 rdreg = mii_send (mk_mii_write (addr, reg, value));
553 printf ("0x%04x\n", value);
558 #endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) */
559 #endif /* CFG_CMD_NET, FEC_ENET */
561 int mcf52x2_miiphy_initialize(bd_t *bis)
563 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
564 #if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
565 miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write);