3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/immap.h>
32 #if defined(CONFIG_CMD_NET)
38 #ifdef CONFIG_MCF5301x
41 volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
42 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
43 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
45 /* watchdog is enabled by default - disable the watchdog */
46 #ifndef CONFIG_WATCHDOG
50 scm1->mpr = 0x77777777;
59 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
60 && defined(CONFIG_SYS_CS0_CTRL))
61 gpio->par_cs |= GPIO_PAR_CS0_CS0;
62 fbcs->csar0 = CONFIG_SYS_CS0_BASE;
63 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
64 fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
67 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
68 && defined(CONFIG_SYS_CS1_CTRL))
69 gpio->par_cs |= GPIO_PAR_CS1_CS1;
70 fbcs->csar1 = CONFIG_SYS_CS1_BASE;
71 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
72 fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
75 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
76 && defined(CONFIG_SYS_CS2_CTRL))
77 fbcs->csar2 = CONFIG_SYS_CS2_BASE;
78 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
79 fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
82 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
83 && defined(CONFIG_SYS_CS3_CTRL))
84 fbcs->csar3 = CONFIG_SYS_CS3_BASE;
85 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
86 fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
89 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
90 && defined(CONFIG_SYS_CS4_CTRL))
91 gpio->par_cs |= GPIO_PAR_CS4;
92 fbcs->csar4 = CONFIG_SYS_CS4_BASE;
93 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
94 fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
97 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
98 && defined(CONFIG_SYS_CS5_CTRL))
99 gpio->par_cs |= GPIO_PAR_CS5;
100 fbcs->csar5 = CONFIG_SYS_CS5_BASE;
101 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
102 fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
105 #ifdef CONFIG_FSL_I2C
106 gpio->par_feci2c = GPIO_PAR_FECI2C_SDA_SDA | GPIO_PAR_FECI2C_SCL_SCL;
112 /* initialize higher level parts of CPU like timers */
116 volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
119 volatile rtc_t *rtc = (rtc_t *) (CONFIG_SYS_MCFRTC_BASE);
120 volatile rtcex_t *rtcex = (rtcex_t *) & rtc->extended;
122 rtcex->gocu = CONFIG_SYS_RTC_CNT;
123 rtcex->gocl = CONFIG_SYS_RTC_SETUP;
127 if (CONFIG_SYS_FEC0_MIIBASE != CONFIG_SYS_FEC1_MIIBASE)
128 ccm->misccr |= CCM_MISCCR_FECM;
130 ccm->misccr &= ~CCM_MISCCR_FECM;
136 void uart_port_conf(void)
138 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
141 switch (CONFIG_SYS_UART_PORT) {
143 gpio->par_uart = (GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
146 #ifdef CONFIG_SYS_UART1_ALT1_GPIO
148 ~(GPIO_PAR_SIMP1H_DATA1_MASK | GPIO_PAR_SIMP1H_VEN1_MASK);
150 (GPIO_PAR_SIMP1H_DATA1_U1TXD | GPIO_PAR_SIMP1H_VEN1_U1RXD);
151 #elif defined(CONFIG_SYS_UART1_ALT2_GPIO)
153 ~(GPIO_PAR_SSIH_RXD_MASK | GPIO_PAR_SSIH_TXD_MASK);
155 (GPIO_PAR_SSIH_RXD_U1RXD | GPIO_PAR_SSIH_TXD_U1TXD);
159 #ifdef CONFIG_SYS_UART2_PRI_GPIO
160 gpio->par_uart |= (GPIO_PAR_UART_U2TXD | GPIO_PAR_UART_U2RXD);
161 #elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
163 ~(GPIO_PAR_DSPIH_SIN_MASK | GPIO_PAR_DSPIH_SOUT_MASK);
165 (GPIO_PAR_DSPIH_SIN_U2RXD | GPIO_PAR_DSPIH_SOUT_U2TXD);
166 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
168 ~(GPIO_PAR_FECI2C_SDA_MASK | GPIO_PAR_FECI2C_SCL_MASK);
170 (GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
176 #if defined(CONFIG_CMD_NET)
177 int fecpin_setclear(struct eth_device *dev, int setclear)
179 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
180 struct fec_info_s *info = (struct fec_info_s *)dev->priv;
183 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
185 GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC;
187 GPIO_PAR_FECI2C_MDC0 | GPIO_PAR_FECI2C_MDIO0;
190 GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC;
192 GPIO_PAR_FECI2C_MDC1 | GPIO_PAR_FECI2C_MDIO1;
195 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
197 ~(GPIO_PAR_FEC0_7W_FEC | GPIO_PAR_FEC0_RMII_FEC);
198 gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII0_MASK;
201 ~(GPIO_PAR_FEC1_7W_FEC | GPIO_PAR_FEC1_RMII_FEC);
202 gpio->par_feci2c &= GPIO_PAR_FECI2C_RMII1_MASK;
207 #endif /* CONFIG_CMD_NET */
208 #endif /* CONFIG_MCF5301x */
210 #ifdef CONFIG_MCF532x
211 void cpu_init_f(void)
213 volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
214 volatile scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
215 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
216 volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
217 volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
219 /* watchdog is enabled by default - disable the watchdog */
220 #ifndef CONFIG_WATCHDOG
224 scm1->mpr0 = 0x77777777;
234 /* Port configuration */
237 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
238 && defined(CONFIG_SYS_CS0_CTRL))
239 fbcs->csar0 = CONFIG_SYS_CS0_BASE;
240 fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
241 fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
244 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
245 && defined(CONFIG_SYS_CS1_CTRL))
246 /* Latch chipselect */
247 gpio->par_cs |= GPIO_PAR_CS1;
248 fbcs->csar1 = CONFIG_SYS_CS1_BASE;
249 fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
250 fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
253 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
254 && defined(CONFIG_SYS_CS2_CTRL))
255 gpio->par_cs |= GPIO_PAR_CS2;
256 fbcs->csar2 = CONFIG_SYS_CS2_BASE;
257 fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
258 fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
261 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
262 && defined(CONFIG_SYS_CS3_CTRL))
263 gpio->par_cs |= GPIO_PAR_CS3;
264 fbcs->csar3 = CONFIG_SYS_CS3_BASE;
265 fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
266 fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
269 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
270 && defined(CONFIG_SYS_CS4_CTRL))
271 gpio->par_cs |= GPIO_PAR_CS4;
272 fbcs->csar4 = CONFIG_SYS_CS4_BASE;
273 fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
274 fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
277 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
278 && defined(CONFIG_SYS_CS5_CTRL))
279 gpio->par_cs |= GPIO_PAR_CS5;
280 fbcs->csar5 = CONFIG_SYS_CS5_BASE;
281 fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
282 fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
285 #ifdef CONFIG_FSL_I2C
286 gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
293 * initialize higher level parts of CPU like timers
300 void uart_port_conf(void)
302 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
305 switch (CONFIG_SYS_UART_PORT) {
307 gpio->par_uart = (GPIO_PAR_UART_TXD0 | GPIO_PAR_UART_RXD0);
311 (GPIO_PAR_UART_TXD1(3) | GPIO_PAR_UART_RXD1(3));
314 gpio->par_timer &= 0x0F;
315 gpio->par_timer |= (GPIO_PAR_TIN3_URXD2 | GPIO_PAR_TIN2_UTXD2);
320 #if defined(CONFIG_CMD_NET)
321 int fecpin_setclear(struct eth_device *dev, int setclear)
323 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
326 gpio->par_fec |= GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC;
328 GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO;
330 gpio->par_fec &= ~(GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
332 ~(GPIO_PAR_FECI2C_MDC_EMDC | GPIO_PAR_FECI2C_MDIO_EMDIO);
337 #endif /* CONFIG_MCF532x */