1 /* Only eth0 supported for now
4 * Thomas.Lange@corelatus.se
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #if defined(CFG_DISCOVER_PHY) || (CONFIG_COMMANDS & CFG_CMD_MII)
29 #error "PHY and MII not supported yet"
30 /* We just assume that we are running 100FD for now */
31 /* We all use switches, right? ;-) */
34 /* I assume ethernet behaves like au1000 */
37 /* Base address differ between cpu:s */
38 #define ETH0_BASE AU1000_ETH0_BASE
39 #define MAC0_ENABLE AU1000_MAC0_ENABLE
42 #define ETH0_BASE AU1100_ETH0_BASE
43 #define MAC0_ENABLE AU1100_MAC0_ENABLE
46 #define ETH0_BASE AU1500_ETH0_BASE
47 #define MAC0_ENABLE AU1500_MAC0_ENABLE
49 #error "No valid cpu set"
59 #include <asm/au1x00.h>
61 /* Ethernet Transmit and Receive Buffers */
62 #define DBUF_LENGTH 1520
63 #define PKT_MAXBUF_SIZE 1518
65 static char txbuf[DBUF_LENGTH];
70 /* 4 rx and 4 tx fifos */
76 u32 len; /* Only used for tx */
80 mac_fifo_t mac_fifo[NO_OF_FIFOS];
84 static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){
85 volatile mac_fifo_t *fifo_tx =
86 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
90 /* tx fifo should always be idle */
91 fifo_tx[next_tx].len = length;
92 fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE;
97 while(!(fifo_tx[next_tx].addr&TX_T_DONE)){
99 printf("TX timeout\n");
107 fifo_tx[next_tx].addr = 0;
108 fifo_tx[next_tx].len = 0;
111 res = fifo_tx[next_tx].status;
114 if(next_tx>=NO_OF_FIFOS){
120 static int au1x00_recv(struct eth_device* dev){
121 volatile mac_fifo_t *fifo_rx =
122 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
128 if(!(fifo_rx[next_rx].addr&RX_T_DONE)){
129 /* Nothing has been received */
133 status = fifo_rx[next_rx].status;
135 length = status&0x3FFF;
138 printf("Rx error 0x%x\n", status);
141 /* Pass the packet up to the protocol layers. */
142 NetReceive(NetRxPackets[next_rx], length - 4);
145 fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE;
148 if(next_rx>=NO_OF_FIFOS){
153 return(0); /* Does anyone use this? */
156 static int au1x00_init(struct eth_device* dev, bd_t * bd){
158 volatile u32 *macen = (volatile u32*)MAC0_ENABLE;
159 volatile u32 *mac_ctrl = (volatile u32*)(ETH0_BASE+MAC_CONTROL);
160 volatile u32 *mac_addr_high = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_HIGH);
161 volatile u32 *mac_addr_low = (volatile u32*)(ETH0_BASE+MAC_ADDRESS_LOW);
162 volatile u32 *mac_mcast_high = (volatile u32*)(ETH0_BASE+MAC_MCAST_HIGH);
163 volatile u32 *mac_mcast_low = (volatile u32*)(ETH0_BASE+MAC_MCAST_LOW);
164 volatile mac_fifo_t *fifo_tx =
165 (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS);
166 volatile mac_fifo_t *fifo_rx =
167 (volatile mac_fifo_t*)(MAC0_RX_DMA_ADDR+MAC_RX_BUFF0_STATUS);
173 /* We have to enable clocks before releasing reset */
174 *macen = MAC_EN_CLOCK_ENABLE;
178 /* We have to release reset before accessing registers */
179 *macen = MAC_EN_CLOCK_ENABLE|MAC_EN_RESET0|
180 MAC_EN_RESET1|MAC_EN_RESET2;
183 for(i=0;i<NO_OF_FIFOS;i++){
185 fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
186 fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE;
189 /* Put mac addr in little endian */
190 #define ea eth_get_dev()->enetaddr
191 *mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
192 *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
193 (ea[1] << 8) | (ea[0] ) ;
198 /* Make sure the MAC buffer is in the correct endian mode */
199 #ifdef __LITTLE_ENDIAN
200 *mac_ctrl = MAC_FULL_DUPLEX;
202 *mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
204 *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
206 *mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
212 static void au1x00_halt(struct eth_device* dev){
215 int au1x00_enet_initialize(bd_t *bis){
216 struct eth_device* dev;
218 dev = (struct eth_device*) malloc(sizeof *dev);
219 memset(dev, 0, sizeof *dev);
221 sprintf(dev->name, "Au1X00 ETHERNET");
224 dev->init = au1x00_init;
225 dev->halt = au1x00_halt;
226 dev->send = au1x00_send;
227 dev->recv = au1x00_recv;
234 #endif /* CONFIG_AU1X00 */