2 * Cache-handling routined for MIPS CPUs
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/regdef.h>
28 #include <asm/mipsregs.h>
29 #include <asm/addrspace.h>
30 #include <asm/cacheops.h>
35 * 16kB is the maximum size of instruction and data caches on MIPS 4K,
36 * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
38 * Note that the above size is the maximum size of primary cache. U-Boot
39 * doesn't have L2 cache support for now.
41 #define MIPS_MAX_CACHE_SIZE 0x10000
43 #define INDEX_BASE CKSEG0
45 .macro cache_op op addr
54 * cacheop macro to automate cache operations
55 * first some helpers...
57 #define _mincache(size, maxsize) \
58 bltu size,maxsize,9f ; \
62 #define _align(minaddr, maxaddr, linesize) \
64 subu AT,linesize,1 ; \
71 /* general operations */
74 #define doop2(op1, op2) \
79 /* specials for cache initialisation */
80 #define doop1lw(op1) \
82 #define doop1lw1(op1) \
86 #define doop121(op1,op2) \
93 #define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
95 10: doop##tag##ops ; \
96 bne minaddr,maxaddr,10b ; \
97 add minaddr,linesize ; \
100 /* finally the cache operation macros */
101 #define vcacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
104 _align(kva, n, cacheLineSize) ; \
105 _oploopn(kva, n, cacheLineSize, tag, ops) ; \
108 #define icacheopn(kva, n, cacheSize, cacheLineSize, tag, ops) \
109 _mincache(n, cacheSize); \
112 _align(kva, n, cacheLineSize) ; \
113 _oploopn(kva, n, cacheLineSize, tag, ops) ; \
116 #define vcacheop(kva, n, cacheSize, cacheLineSize, op) \
117 vcacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
119 #define icacheop(kva, n, cacheSize, cacheLineSize, op) \
120 icacheopn(kva, n, cacheSize, cacheLineSize, 1, (op))
122 .macro f_fill64 dst, offset, val
123 LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
124 LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
125 LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
126 LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
127 LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
128 LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
129 LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
130 LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
132 LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
133 LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
134 LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
135 LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
136 LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
137 LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
138 LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
139 LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
144 * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
146 LEAF(mips_init_icache)
149 /* clear tag to invalidate */
150 PTR_LI t0, INDEX_BASE
152 1: cache_op Index_Store_Tag_I t0
155 /* fill once, so data field parity is correct */
156 PTR_LI t0, INDEX_BASE
160 /* invalidate again - prudent but not strictly neccessary */
161 PTR_LI t0, INDEX_BASE
162 1: cache_op Index_Store_Tag_I t0
166 END(mips_init_icache)
169 * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
171 LEAF(mips_init_dcache)
175 PTR_LI t0, INDEX_BASE
177 1: cache_op Index_Store_Tag_D t0
180 /* load from each line (in cached space) */
181 PTR_LI t0, INDEX_BASE
182 2: LONG_L zero, 0(t0)
186 PTR_LI t0, INDEX_BASE
187 1: cache_op Index_Store_Tag_D t0
191 END(mips_init_dcache)
193 /*******************************************************************************
195 * mips_cache_reset - low level initialisation of the primary caches
197 * This routine initialises the primary caches to ensure that they
198 * have good parity. It must be called by the ROM before any cached locations
199 * are used to prevent the possibility of data with bad parity being written to
201 * To initialise the instruction cache it is essential that a source of data
202 * with good parity is available. This routine
203 * will initialise an area of memory starting at location zero to be used as
204 * a source of parity.
209 NESTED(mips_cache_reset, 0, ra)
211 li t2, CFG_ICACHE_SIZE
212 li t3, CFG_DCACHE_SIZE
213 li t4, CFG_CACHELINE_SIZE
216 li v0, MIPS_MAX_CACHE_SIZE
219 * Now clear that much memory starting from zero.
224 f_fill64 a0, -64, zero
228 * The caches are probably in an indeterminate state,
229 * so we force good parity into them by doing an
230 * invalidate, load/fill, invalidate for each line.
234 * Assume bottom of RAM will generate good parity for the cache.
238 * Initialize the I-cache first,
242 PTR_LA t7, mips_init_icache
246 * then initialize D-cache.
250 PTR_LA t7, mips_init_dcache
254 END(mips_cache_reset)
256 /*******************************************************************************
258 * dcache_status - get cache status
260 * RETURNS: 0 - cache disabled; 1 - cache enabled
265 li t1, CONF_CM_UNCACHED
266 andi t0, t0, CONF_CM_CMASK
273 /*******************************************************************************
275 * dcache_disable - disable cache
284 ori t0, t0, CONF_CM_UNCACHED
289 /*******************************************************************************
291 * dcache_enable - enable cache
298 ori t0, CONF_CM_CMASK
299 xori t0, CONF_CM_CMASK
300 ori t0, CONF_CM_CACHABLE_NONCOHERENT
305 #ifdef CFG_INIT_RAM_LOCK_MIPS
306 /*******************************************************************************
308 * mips_cache_lock - lock RAM area pointed to by a0 in cache.
313 #if defined(CONFIG_PURPLE)
314 # define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
316 # define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
318 .globl mips_cache_lock
321 li a1, CKSEG0 - CACHE_LOCK_SIZE
323 li a2, CACHE_LOCK_SIZE
324 li a3, CFG_CACHELINE_SIZE
326 icacheop(a0,a1,a2,a3,0x1d)
331 #endif /* CFG_INIT_RAM_LOCK_MIPS */