2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
3 * (C) Copyright 2007 DENX Software Engineering
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * CPU specific code for the MPC512x family.
27 * Derived from the MPC83xx code.
34 #include <asm/processor.h>
36 #if defined(CONFIG_OF_LIBFDT)
37 #include <fdt_support.h>
40 DECLARE_GLOBAL_DATA_PTR;
44 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
45 ulong clock = gd->cpu_clk;
47 u32 spridr = immr->sysconf.spridr;
48 char buf1[32], buf2[32];
52 switch (spridr & 0xffff0000) {
57 printf ("Unknown part ID %08x ", spridr & 0xffff0000);
59 printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr));
61 switch (pvr & 0xffff0000) {
68 printf ("at %s MHz, CSB at %s MHz\n",
70 strmhz(buf2, gd->csb_clk) );
76 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
79 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
81 /* Interrupts and MMU off */
82 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
84 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
85 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
88 * Enable Reset Control Reg - "RSTE" is the magic word that let us go
90 immap->reset.rpr = 0x52535445;
92 /* Verify Reset Control Reg is enabled */
93 while (!((immap->reset.rcer) & RCER_CRE))
96 printf ("Resetting the board.\n");
100 immap->reset.rcr = RCR_SWHR;
108 * Get timebase clock frequency (like cpu_clk in Hz)
110 unsigned long get_tbclk (void)
114 tbclk = (gd->bus_clk + 3L) / 4L;
120 #if defined(CONFIG_WATCHDOG)
121 void watchdog_reset (void)
123 int re_enable = disable_interrupts ();
126 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
127 immr->wdt.swsrr = 0x556c;
128 immr->wdt.swsrr = 0xaa39;
131 enable_interrupts ();
135 #ifdef CONFIG_OF_LIBFDT
137 #ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
139 * fdt setup for old device trees
145 static void old_ft_cpu_setup(void *blob, bd_t *bd)
148 * avoid fixing up by path because that
149 * produces scary error messages
153 * old device trees have ethernet nodes with
154 * device_type = "network"
156 do_fixup_by_prop(blob, "device_type", "network", 8,
157 "local-mac-address", bd->bi_enetaddr, 6, 0);
158 do_fixup_by_prop(blob, "device_type", "network", 8,
159 "address", bd->bi_enetaddr, 6, 0);
161 * old device trees have soc nodes with
162 * device_type = "soc"
164 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
165 "bus-frequency", bd->bi_ipsfreq, 0);
169 static void ft_clock_setup(void *blob, bd_t *bd)
171 char *cpu_path = "/cpus/" OF_CPU;
174 * fixup cpu clocks using path
176 do_fixup_by_path_u32(blob, cpu_path,
177 "timebase-frequency", OF_TBCLK, 1);
178 do_fixup_by_path_u32(blob, cpu_path,
179 "bus-frequency", bd->bi_busfreq, 1);
180 do_fixup_by_path_u32(blob, cpu_path,
181 "clock-frequency", bd->bi_intfreq, 1);
183 * fixup soc clocks using compatible
185 do_fixup_by_compat_u32(blob, OF_SOC_COMPAT,
186 "bus-frequency", bd->bi_ipsfreq, 1);
189 void ft_cpu_setup(void *blob, bd_t *bd)
191 #ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
192 old_ft_cpu_setup(blob, bd);
194 ft_clock_setup(blob, bd);
195 #ifdef CONFIG_HAS_ETH0
196 fdt_fixup_ethernet(blob);
201 #ifdef CONFIG_MPC512x_FEC
202 /* Default initializations for FEC controllers. To override,
203 * create a board-specific function called:
204 * int board_eth_init(bd_t *bis)
207 int cpu_eth_init(bd_t *bis)
209 return mpc512x_fec_initialize(bis);