2 * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
25 * Discription: Contains initialisation functions to setup
35 * Setup essential cpu registers to run
37 void cpu_init_f (volatile immap_t * immr)
39 volatile memctl5xx_t *memctl = &immr->im_memctl;
42 /* SYPCR - contains watchdog control. This will enable watchdog */
43 /* if CONFIG_WATCHDOG is set */
44 immr->im_siu_conf.sc_sypcr = CFG_SYPCR;
46 #if defined(CONFIG_WATCHDOG)
47 reset_5xx_watchdog (immr);
50 /* SIUMCR - contains debug pin configuration */
51 immr->im_siu_conf.sc_siumcr |= CFG_SIUMCR;
53 /* Initialize timebase. Unlock TBSCRK */
54 immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
55 immr->im_sit.sit_tbscr = CFG_TBSCR;
57 /* Full IMB bus speed */
58 immr->im_uimb.uimb_umcr = CFG_UMCR;
60 /* Time base and decrementer will be enables (TBE) */
61 /* in init_timebase() in time.c called from board_init_f(). */
63 /* Initialize the PIT. Unlock PISCRK */
64 immr->im_sitk.sitk_piscrk = KAPWR_KEY;
65 immr->im_sit.sit_piscr = CFG_PISCR;
67 /* PLL (CPU clock) settings */
68 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
70 /* If CFG_PLPRCR (set in the various *_config.h files) tries to
71 * set the MF field, then just copy CFG_PLPRCR over car_plprcr,
72 * otherwise OR in CFG_PLPRCR so we do not change the currentMF
75 #if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0)
76 reg = CFG_PLPRCR; /* reset control bits */
78 reg = immr->im_clkrst.car_plprcr;
79 reg &= PLPRCR_MF_MSK; /* isolate MF field */
80 reg |= CFG_PLPRCR; /* reset control bits */
82 immr->im_clkrst.car_plprcr = reg;
84 /* System integration timers. CFG_MASK has EBDF configuration */
85 immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
86 reg = immr->im_clkrst.car_sccr;
89 immr->im_clkrst.car_sccr = reg;
91 /* Memory Controller */
92 memctl->memc_br0 = CFG_BR0_PRELIM;
93 memctl->memc_or0 = CFG_OR0_PRELIM;
95 #if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
96 memctl->memc_or1 = CFG_OR1_PRELIM;
97 memctl->memc_br1 = CFG_BR1_PRELIM;
100 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
101 memctl->memc_or2 = CFG_OR2_PRELIM;
102 memctl->memc_br2 = CFG_BR2_PRELIM;
105 #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
106 memctl->memc_or3 = CFG_OR3_PRELIM;
107 memctl->memc_br3 = CFG_BR3_PRELIM;
113 * Initialize higher level parts of cpu
115 int cpu_init_r (void)
117 /* Nothing to do at the moment */