3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
17 /* #define DEBUG 0x28 */
19 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
20 defined(CONFIG_MPC5XXX_FEC)
23 static void tfifo_print(mpc5xxx_fec_priv *fec);
24 static void rfifo_print(mpc5xxx_fec_priv *fec);
28 static uint32 local_crc32(char *string, unsigned int crc_value, int len);
32 uint8 data[1500]; /* actual data */
33 int length; /* actual length */
34 int used; /* buffer in use or not */
35 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
38 /********************************************************************/
39 static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
45 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
47 data = (char *)malloc(FEC_MAX_PKT_SIZE);
49 printf ("RBD INIT FAILED\n");
52 fec->rbdBase[ix].dataPointer = (uint32)data;
54 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
55 fec->rbdBase[ix].dataLength = 0;
60 * have the last RBD to close the ring
62 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
68 /********************************************************************/
69 static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
73 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
74 fec->tbdBase[ix].status = 0;
78 * Have the last TBD to close the ring
80 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
83 * Initialize some indices
86 fec->usedTbdIndex = 0;
87 fec->cleanTbdNum = FEC_TBD_NUM;
90 /********************************************************************/
91 static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, FEC_RBD * pRbd)
94 * Reset buffer descriptor as empty
96 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
97 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
99 pRbd->status = FEC_RBD_EMPTY;
101 pRbd->dataLength = 0;
104 * Now, we have an empty RxBD, restart the SmartDMA receive task
106 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
111 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
114 /********************************************************************/
115 static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
120 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
121 fec->cleanTbdNum, fec->usedTbdIndex);
125 * process all the consumed TBDs
127 while (fec->cleanTbdNum < FEC_TBD_NUM) {
128 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
129 if (pUsedTbd->status & FEC_TBD_READY) {
131 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
137 * clean this buffer descriptor
139 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
140 pUsedTbd->status = FEC_TBD_WRAP;
142 pUsedTbd->status = 0;
145 * update some indeces for a correct handling of the TBD ring
148 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
152 /********************************************************************/
153 static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
155 uint8 currByte; /* byte for which to compute the CRC */
156 int byte; /* loop - counter */
157 int bit; /* loop - counter */
158 uint32 crc = 0xffffffff; /* initial value */
161 * The algorithm used is the following:
162 * we loop on each of the six bytes of the provided address,
163 * and we compute the CRC by left-shifting the previous
164 * value by one position, so that each bit in the current
165 * byte of the address may contribute the calculation. If
166 * the latter and the MSB in the CRC are different, then
167 * the CRC value so computed is also ex-ored with the
168 * "polynomium generator". The current byte of the address
169 * is also shifted right by one bit at each iteration.
170 * This is because the CRC generatore in hardware is implemented
171 * as a shift-register with as many ex-ores as the radixes
172 * in the polynomium. This suggests that we represent the
173 * polynomiumm itself as a 32-bit constant.
175 for (byte = 0; byte < 6; byte++) {
176 currByte = mac[byte];
177 for (bit = 0; bit < 8; bit++) {
178 if ((currByte & 0x01) ^ (crc & 0x01)) {
180 crc = crc ^ 0xedb88320;
191 * Set individual hash table register
194 fec->eth->iaddr1 = (1 << (crc - 32));
195 fec->eth->iaddr2 = 0;
197 fec->eth->iaddr1 = 0;
198 fec->eth->iaddr2 = (1 << crc);
202 * Set physical address
204 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
205 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
208 /********************************************************************/
209 static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
211 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
212 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
213 const uint8 phyAddr = 0; /* Only one PHY */
216 printf ("mpc5xxx_fec_init... Begin\n");
220 * Initialize RxBD/TxBD rings
222 mpc5xxx_fec_rbd_init(fec);
223 mpc5xxx_fec_tbd_init(fec);
226 * Initialize GPIO pins
228 if (fec->xcv_type == SEVENWIRE) {
229 /* 10MBit with 7-wire operation */
230 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
232 /* 100MBit with MD operation */
233 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
237 * Clear FEC-Lite interrupt event register(IEVENT)
239 fec->eth->ievent = 0xffffffff;
242 * Set interrupt mask register
244 fec->eth->imask = 0x00000000;
247 * Set FEC-Lite receive control register(R_CNTRL):
249 if (fec->xcv_type == SEVENWIRE) {
251 * Frame length=1518; 7-wire mode
253 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
256 * Frame length=1518; MII mode;
258 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
261 if (fec->xcv_type == SEVENWIRE) {
263 * Set FEC-Lite transmit control register(X_CNTRL):
265 /*fec->eth->x_cntrl = 0x00000002; */ /* half-duplex, heartbeat */
266 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
268 /*fec->eth->x_cntrl = 0x00000006; */ /* full-duplex, heartbeat */
269 fec->eth->x_cntrl = 0x00000004; /* full-duplex, heartbeat disabled */
272 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock(25Mhz)
273 * and do not drop the Preamble.
275 fec->eth->mii_speed = (0x5 << 1); /* No MII for 7-wire mode */
279 * Set Opcode/Pause Duration Register
281 fec->eth->op_pause = 0x00010020; /*FIXME0xffff0020; */
284 * Set Rx FIFO alarm and granularity value
286 fec->eth->rfifo_cntrl = 0x0c000000;
287 fec->eth->rfifo_alarm = 0x0000030c;
289 if (fec->eth->rfifo_status & 0x00700000 ) {
290 printf("mpc5xxx_fec_init() RFIFO error\n");
295 * Set Tx FIFO granularity value
297 fec->eth->tfifo_cntrl = 0x0c000000;
299 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
300 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
304 * Set transmit fifo watermark register(X_WMRK), default = 64
306 fec->eth->tfifo_alarm = 0x00000080;
307 fec->eth->x_wmrk = 0x2;
310 * Set individual address filter for unicast address
311 * and set physical address registers.
313 mpc5xxx_fec_set_hwaddr(fec, dev->enetaddr);
316 * Set multicast address filter
318 fec->eth->gaddr1 = 0x00000000;
319 fec->eth->gaddr2 = 0x00000000;
322 * Turn ON cheater FSM: ????
324 fec->eth->xmit_fsm = 0x03000000;
326 #if defined(CONFIG_MPC5200)
328 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
329 * work w/ the current receive task.
331 sdma->PtdCntrl |= 0x00000001;
335 * Set priority of different initiators
337 sdma->IPR0 = 7; /* always */
338 sdma->IPR3 = 6; /* Eth RX */
339 sdma->IPR4 = 5; /* Eth Tx */
342 * Clear SmartDMA task interrupt pending bits
344 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
347 * Initialize SmartDMA parameters stored in SRAM
349 *(int *)FEC_TBD_BASE = (int)fec->tbdBase;
350 *(int *)FEC_RBD_BASE = (int)fec->rbdBase;
351 *(int *)FEC_TBD_NEXT = (int)fec->tbdBase;
352 *(int *)FEC_RBD_NEXT = (int)fec->rbdBase;
354 if (fec->xcv_type != SEVENWIRE) {
356 * Initialize PHY(LXT971A):
358 * Generally, on power up, the LXT971A reads its configuration
359 * pins to check for forced operation, If not cofigured for
360 * forced operation, it uses auto-negotiation/parallel detection
361 * to automatically determine line operating conditions.
362 * If the PHY device on the other side of the link supports
363 * auto-negotiation, the LXT971A auto-negotiates with it
364 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
365 * support auto-negotiation, the LXT971A automatically detects
366 * the presence of either link pulses(10Mbps PHY) or Idle
367 * symbols(100Mbps) and sets its operating conditions accordingly.
369 * When auto-negotiation is controlled by software, the following
370 * steps are recommended.
373 * The physical address is dependent on hardware configuration.
380 * Reset PHY, then delay 300ns
382 miiphy_write(phyAddr, 0x0, 0x8000);
385 if (fec->xcv_type == MII10) {
387 * Force 10Base-T, FDX operation
389 printf("Forcing 10 Mbps ethernet link... ");
390 miiphy_read(phyAddr, 0x1, &phyStatus);
392 miiphy_write(fec, phyAddr, 0x0, 0x0100);
394 miiphy_write(phyAddr, 0x0, 0x0180);
397 do { /* wait for link status to go down */
399 if ((timeout--) == 0) {
401 printf("hmmm, should not have waited...");
405 miiphy_read(phyAddr, 0x1, &phyStatus);
409 } while ((phyStatus & 0x0004)); /* !link up */
412 do { /* wait for link status to come back up */
414 if ((timeout--) == 0) {
415 printf("failed. Link is down.\n");
418 miiphy_read(phyAddr, 0x1, &phyStatus);
422 } while (!(phyStatus & 0x0004)); /* !link up */
425 } else { /* MII100 */
427 * Set the auto-negotiation advertisement register bits
429 miiphy_write(phyAddr, 0x4, 0x01e1);
432 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
434 miiphy_write(phyAddr, 0x0, 0x1200);
437 * Wait for AN completion
443 if ((timeout--) == 0) {
445 printf("PHY auto neg 0 failed...\n");
450 if (miiphy_read(phyAddr, 0x1, &phyStatus) != 0) {
452 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
456 } while ((phyStatus & 0x0020) != 0x0020);
459 printf("PHY auto neg complete! \n");
466 * Enable FEC-Lite controller
468 fec->eth->ecntrl |= 0x00000006;
470 if (fec->xcv_type != SEVENWIRE) {
475 for (i = 0; i < 9; i++) {
476 miiphy_read(phyAddr, i, &phyStatus);
477 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
479 for (i = 16; i < 21; i++) {
480 miiphy_read(phyAddr, i, &phyStatus);
481 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
486 * Enable SmartDMA receive task
488 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
491 printf("mpc5xxx_fec_init... Done \n");
497 /********************************************************************/
498 static void mpc5xxx_fec_halt(struct eth_device *dev)
500 #if defined(CONFIG_MPC5200)
501 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
503 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
504 int counter = 0xffff;
507 if (fec->xcv_type != SEVENWIRE) {
511 for (i = 0; i < 9; i++) {
512 miiphy_read(phyAddr, i, &phyStatus);
513 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
515 for (i = 16; i < 21; i++) {
516 miiphy_read(phyAddr, i, &phyStatus);
517 printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
524 * mask FEC chip interrupts
529 * issue graceful stop command to the FEC transmitter if necessary
531 fec->eth->x_cntrl |= 0x00000001;
534 * wait for graceful stop to register
536 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
539 * Disable SmartDMA tasks
541 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
542 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
544 #if defined(CONFIG_MPC5200)
546 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
547 * done. It doesn't work w/ the current receive task.
549 sdma->PtdCntrl &= ~0x00000001;
553 * Disable the Ethernet Controller
555 fec->eth->ecntrl &= 0xfffffffd;
558 * Clear FIFO status registers
560 fec->eth->rfifo_status &= 0x00700000;
561 fec->eth->tfifo_status &= 0x00700000;
563 fec->eth->reset_cntrl = 0x01000000;
566 * Issue a reset command to the FEC chip
568 fec->eth->ecntrl |= 0x1;
571 * wait at least 16 clock cycles
576 printf("Ethernet task stopped\n");
581 /********************************************************************/
583 static void tfifo_print(mpc5xxx_fec_priv *fec)
588 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
589 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
591 miiphy_read(phyAddr, 0x1, &phyStatus);
592 printf("\nphyStatus: 0x%04x\n", phyStatus);
593 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
594 printf("ievent: 0x%08x\n", fec->eth->ievent);
595 printf("x_status: 0x%08x\n", fec->eth->x_status);
596 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
598 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
599 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
600 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
601 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
602 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
603 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
607 static void rfifo_print(mpc5xxx_fec_priv *fec)
612 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
613 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
615 miiphy_read(phyAddr, 0x1, &phyStatus);
616 printf("\nphyStatus: 0x%04x\n", phyStatus);
617 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
618 printf("ievent: 0x%08x\n", fec->eth->ievent);
619 printf("x_status: 0x%08x\n", fec->eth->x_status);
620 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
622 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
623 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
624 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
625 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
626 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
627 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
632 /********************************************************************/
634 static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
638 * This routine transmits one frame. This routine only accepts
639 * 6-byte Ethernet addresses.
641 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
645 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
650 * Clear Tx BD ring at first
652 mpc5xxx_fec_tbd_scrub(fec);
655 * Check for valid length of data.
657 if ((data_length > 1500) || (data_length <= 0)) {
662 * Check the number of vacant TxBDs.
664 if (fec->cleanTbdNum < 1) {
666 printf("No available TxBDs ...\n");
672 * Get the first TxBD to send the mac header
674 pTbd = &fec->tbdBase[fec->tbdIndex];
675 pTbd->dataLength = data_length;
676 pTbd->dataPointer = (uint32)eth_data;
677 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
678 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
681 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
687 if (fec->xcv_type != SEVENWIRE) {
689 miiphy_read(0, 0x1, &phyStatus);
693 * Enable SmartDMA transmit task
699 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
707 fec->cleanTbdNum -= 1;
709 #if (DEBUG & 0x129) && (DEBUG & 0x80000000)
710 printf ("smartDMA ethernet Tx task enabled\n");
713 * wait until frame is sent .
715 while (pTbd->status & FEC_TBD_READY) {
718 printf ("TDB status = %04x\n", pTbd->status);
726 /********************************************************************/
727 static int mpc5xxx_fec_recv(struct eth_device *dev)
730 * This command pulls one frame from the card
732 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
733 FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
734 unsigned long ievent;
735 int frame_length, len = 0;
737 char buff[FEC_MAX_PKT_SIZE];
740 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
747 * Check if any critical events have happened
749 ievent = fec->eth->ievent;
750 fec->eth->ievent = ievent;
751 if (ievent & 0x20060000) {
752 /* BABT, Rx/Tx FIFO errors */
753 mpc5xxx_fec_halt(dev);
754 mpc5xxx_fec_init(dev, NULL);
757 if (ievent & 0x80000000) {
758 /* Heartbeat error */
759 fec->eth->x_cntrl |= 0x00000001;
761 if (ievent & 0x10000000) {
762 /* Graceful stop complete */
763 if (fec->eth->x_cntrl & 0x00000001) {
764 mpc5xxx_fec_halt(dev);
765 fec->eth->x_cntrl &= ~0x00000001;
766 mpc5xxx_fec_init(dev, NULL);
770 if (!(pRbd->status & FEC_RBD_EMPTY)) {
771 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
772 ((pRbd->dataLength - 4) > 14)) {
775 * Get buffer address and size
777 frame = (NBUF *)pRbd->dataPointer;
778 frame_length = pRbd->dataLength - 4;
783 printf("recv data hdr:");
784 for (i = 0; i < 14; i++)
785 printf("%x ", *(frame->head + i));
790 * Fill the buffer and pass it to upper layers
792 memcpy(buff, frame->head, 14);
793 memcpy(buff + 14, frame->data, frame_length);
794 NetReceive(buff, frame_length);
798 * Reset buffer descriptor as empty
800 mpc5xxx_fec_rbd_clean(fec, pRbd);
802 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
807 /********************************************************************/
808 int mpc5xxx_fec_initialize(bd_t * bis)
810 mpc5xxx_fec_priv *fec;
811 struct eth_device *dev;
813 char env_enetaddr[6];
816 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
817 dev = (struct eth_device *)malloc(sizeof(*dev));
818 memset(dev, 0, sizeof *dev);
820 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
821 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
822 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
823 #ifdef CONFIG_ICECUBE
824 fec->xcv_type = MII100;
827 dev->priv = (void *)fec;
828 dev->iobase = MPC5XXX_FEC;
829 dev->init = mpc5xxx_fec_init;
830 dev->halt = mpc5xxx_fec_halt;
831 dev->send = mpc5xxx_fec_send;
832 dev->recv = mpc5xxx_fec_recv;
834 sprintf(dev->name, "FEC ETHERNET");
838 * Try to set the mac address now. The fec mac address is
839 * a garbage after reset. When not using fec for booting
840 * the Linux fec driver will try to work with this garbage.
842 tmp = getenv("ethaddr");
844 for (i=0; i<6; i++) {
845 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
847 tmp = (*end) ? end+1 : end;
849 mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
855 /* MII-interface related functions */
856 /********************************************************************/
857 int miiphy_read(uint8 phyAddr, uint8 regAddr, uint16 * retVal)
859 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
860 uint32 reg; /* convenient holder for the PHY register */
861 uint32 phy; /* convenient holder for the PHY */
862 int timeout = 0xffff;
865 * reading from any PHY's register is done by properly
866 * programming the FEC's MII data register.
868 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
869 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
871 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
874 * wait for the related interrupt
876 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
880 printf ("Read MDIO failed...\n");
886 * clear mii interrupt bit
888 eth->ievent = 0x00800000;
891 * it's now safe to read the PHY's register
893 *retVal = (uint16) eth->mii_data;
898 /********************************************************************/
899 int miiphy_write(uint8 phyAddr, uint8 regAddr, uint16 data)
901 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
902 uint32 reg; /* convenient holder for the PHY register */
903 uint32 phy; /* convenient holder for the PHY */
904 int timeout = 0xffff;
906 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
907 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
909 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
910 FEC_MII_DATA_TA | phy | reg | data);
913 * wait for the MII interrupt
915 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
919 printf ("Write MDIO failed...\n");
925 * clear MII interrupt bit
927 eth->ievent = 0x00800000;
933 static uint32 local_crc32(char *string, unsigned int crc_value, int len)
937 unsigned int crc, count;
943 * crc = 0xffffffff; * The initialized value should be 0xffffffff
947 for (i = len; --i >= 0;) {
949 for (count = 0; count < 8; count++) {
950 if ((c & 0x01) ^ (crc & 0x01)) {
952 crc = crc ^ 0xedb88320;
961 * In big endian system, do byte swaping for crc value
967 #endif /* CONFIG_MPC5XXX_FEC */