2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * U-Boot - Startup Code for MPC5xxx CPUs
32 #define CONFIG_MPC5XXX 1 /* needed for Linux kernel header files */
33 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
35 #include <ppc_asm.tmpl>
38 #include <asm/cache.h>
41 #ifndef CONFIG_IDENT_STRING
42 #define CONFIG_IDENT_STRING ""
45 /* We don't want the MMU yet.
48 /* Floating Point enable, Machine Check and Recoverable Interr. */
50 #define MSR_KERNEL (MSR_FP|MSR_RI)
52 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
56 * Set up GOT: Global Offset Table
58 * Use r14 to access the GOT
61 GOT_ENTRY(_GOT2_TABLE_)
62 GOT_ENTRY(_FIXUP_TABLE_)
65 GOT_ENTRY(_start_of_vectors)
66 GOT_ENTRY(_end_of_vectors)
67 GOT_ENTRY(transfer_to_handler)
71 GOT_ENTRY(__bss_start)
81 .ascii " (", __DATE__, " - ", __TIME__, ")"
82 .ascii CONFIG_IDENT_STRING, "\0"
91 li r21, BOOTFLAG_COLD /* Normal Power-On */
95 . = EXC_OFF_SYS_RESET + 0x10
99 li r21, BOOTFLAG_WARM /* Software reboot */
104 mfmsr r5 /* save msr contents */
106 #if defined(CFG_LOWBOOT)
107 lis r4, CFG_DEFAULT_MBAR@h
109 ori r3, r3, 0x0000FF00@l
112 ori r3, r3, 0x0000FFFF@l
115 ori r3, r3, 0x00047800@l
118 ori r3, r3, 0x02010000@l
121 lis r3, lowboot_reentry@h
122 ori r3, r3, lowboot_reentry@l
124 blr /* jump to flash based address */
128 ori r3, r3, 0x0000FF00@l
131 ori r3, r3, 0x0000FFFF@l
134 ori r3, r3, 0x00047800@l
137 ori r3, r3, 0x02000001@l
139 #endif /* CFG_LOWBOOT */
141 #if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
143 ori r3, r3, CFG_MBAR@l
144 #if defined(CONFIG_MPC5200)
145 rlwinm r3, r3, 16, 16, 31
147 #if defined(CONFIG_MGT5100)
148 rlwinm r3, r3, 17, 15, 31
150 lis r4, CFG_DEFAULT_MBAR@h
152 #endif /* CFG_DEFAULT_MBAR */
154 /* Initialise the MPC5xxx processor core */
155 /*--------------------------------------------------------------*/
159 /* initialize some things that are hard to access from C */
160 /*--------------------------------------------------------------*/
162 /* set up stack in on-chip SRAM */
163 lis r3, CFG_INIT_RAM_ADDR@h
164 ori r3, r3, CFG_INIT_RAM_ADDR@l
165 ori r1, r3, CFG_INIT_SP_OFFSET
166 li r0, 0 /* Make room for stack frame header and */
167 stwu r0, -4(r1) /* clear final stack frame so that */
168 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
170 /* let the C-code set up the rest */
172 /* Be careful to keep code relocatable ! */
173 /*--------------------------------------------------------------*/
175 GET_GOT /* initialize GOT access */
178 bl cpu_init_f /* run low-level CPU init code (in Flash)*/
182 bl board_init_f /* run 1st part of board init code (in Flash)*/
188 .globl _start_of_vectors
192 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
194 /* Data Storage exception. */
195 STD_EXCEPTION(0x300, DataStorage, UnknownException)
197 /* Instruction Storage exception. */
198 STD_EXCEPTION(0x400, InstStorage, UnknownException)
200 /* External Interrupt exception. */
201 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
203 /* Alignment exception. */
211 addi r3,r1,STACK_FRAME_OVERHEAD
213 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
214 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
215 lwz r6,GOT(transfer_to_handler)
219 .long AlignmentException - _start + EXC_OFF_SYS_RESET
220 .long int_return - _start + EXC_OFF_SYS_RESET
222 /* Program check exception */
226 addi r3,r1,STACK_FRAME_OVERHEAD
228 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
229 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
230 lwz r6,GOT(transfer_to_handler)
234 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
235 .long int_return - _start + EXC_OFF_SYS_RESET
237 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
239 /* I guess we could implement decrementer, and may have
240 * to someday for timekeeping.
242 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
244 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
245 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
246 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
247 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
249 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
250 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
252 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
253 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
254 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
258 * This exception occurs when the program counter matches the
259 * Instruction Address Breakpoint Register (IABR).
261 * I want the cpu to halt if this occurs so I can hunt around
262 * with the debugger and look at things.
264 * When DEBUG is defined, both machine check enable (in the MSR)
265 * and checkstop reset enable (in the reset mode register) are
266 * turned off and so a checkstop condition will result in the cpu
269 * I force the cpu into a checkstop condition by putting an illegal
270 * instruction here (at least this is the theory).
272 * well - that didnt work, so just do an infinite loop!
276 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
278 STD_EXCEPTION(0x1400, SMI, UnknownException)
280 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
281 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
282 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
283 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
284 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
285 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
286 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
287 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
288 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
289 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
290 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
291 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
292 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
293 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
294 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
295 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
296 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
297 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
298 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
299 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
300 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
301 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
302 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
303 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
304 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
305 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
306 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
309 .globl _end_of_vectors
315 * This code finishes saving the registers to the exception frame
316 * and jumps to the appropriate handler for the exception.
317 * Register r21 is pointer into trap frame, r1 has new stack pointer.
319 .globl transfer_to_handler
330 andi. r24,r23,0x3f00 /* get vector offset */
334 lwz r24,0(r23) /* virtual address of handler */
335 lwz r23,4(r23) /* where to go when done */
340 rfi /* jump to handler, enable MMU */
343 mfmsr r28 /* Disable interrupts */
347 SYNC /* Some chip revs need this... */
362 lwz r2,_NIP(r1) /* Restore environment */
373 * This code initialises the MPC5xxx processor core
374 * (conforms to PowerPC 603e spec)
375 * Note: expects original MSR contents to be in r5.
381 /* Initialize machine status; enable machine check interrupt */
382 /*--------------------------------------------------------------*/
384 li r3, MSR_KERNEL /* Set ME and RI flags */
385 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
387 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
389 SYNC /* Some chip revs need this... */
392 mtspr SRR1, r3 /* Make SRR1 match MSR */
394 /* Initialize the Hardware Implementation-dependent Registers */
395 /* HID0 also contains cache control */
396 /*--------------------------------------------------------------*/
398 lis r3, CFG_HID0_INIT@h
399 ori r3, r3, CFG_HID0_INIT@l
403 lis r3, CFG_HID0_FINAL@h
404 ori r3, r3, CFG_HID0_FINAL@l
408 /* clear all BAT's */
409 /*--------------------------------------------------------------*/
446 /* invalidate all tlb's */
448 /* From the 603e User Manual: "The 603e provides the ability to */
449 /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
450 /* instruction invalidates the TLB entry indexed by the EA, and */
451 /* operates on both the instruction and data TLBs simultaneously*/
452 /* invalidating four TLB entries (both sets in each TLB). The */
453 /* index corresponds to bits 15-19 of the EA. To invalidate all */
454 /* entries within both TLBs, 32 tlbie instructions should be */
455 /* issued, incrementing this field by one each time." */
457 /* "Note that the tlbia instruction is not implemented on the */
460 /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
461 /* incrementing by 0x1000 each time. The code below is sort of */
462 /* based on code in "flush_tlbs" from arch/ppc/kernel/head.S */
464 /*--------------------------------------------------------------*/
475 /*--------------------------------------------------------------*/
481 * Note: requires that all cache bits in
482 * HID0 are in the low half word.
489 ori r4, r4, HID0_ILOCK
491 ori r4, r3, HID0_ICFI
493 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
495 mtspr HID0, r3 /* clears invalidate */
498 .globl icache_disable
502 ori r4, r4, HID0_ICE|HID0_ILOCK
504 ori r4, r3, HID0_ICFI
506 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
508 mtspr HID0, r3 /* clears invalidate */
514 rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
522 ori r4, r4, HID0_DLOCK
526 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
528 mtspr HID0, r3 /* clears invalidate */
531 .globl dcache_disable
535 ori r4, r4, HID0_DCE|HID0_DLOCK
539 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
541 mtspr HID0, r3 /* clears invalidate */
547 rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
555 /*------------------------------------------------------------------------------*/
558 * void relocate_code (addr_sp, gd, addr_moni)
560 * This "function" does not return, instead it continues in RAM
561 * after relocating the monitor code.
565 * r5 = length in bytes
570 mr r1, r3 /* Set new stack pointer */
571 mr r9, r4 /* Save copy of Global Data pointer */
572 mr r10, r5 /* Save copy of Destination Address */
574 mr r3, r5 /* Destination Address */
575 lis r4, CFG_MONITOR_BASE@h /* Source Address */
576 ori r4, r4, CFG_MONITOR_BASE@l
577 lwz r5, GOT(__init_end)
579 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
584 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
590 /* First our own GOT */
592 /* then the one used by the C code */
602 beq cr1,4f /* In place copy is not necessary */
603 beq 7f /* Protect against 0 count */
622 * Now flush the cache: note that we must start from a cache aligned
623 * address. Otherwise we might miss one cache line.
627 beq 7f /* Always flush prefetch queue in any case */
630 mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
631 rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
639 sync /* Wait for all dcbst to complete on bus */
640 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
641 rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
649 7: sync /* Wait for all icbi to complete on bus */
653 * We are done. Do not return, instead branch to second part of board
654 * initialization, now running from RAM.
657 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
664 * Relocation Function, r14 point to got2+0x8000
666 * Adjust got2 pointers, no need to check for 0, this code
667 * already puts a few entries in the table.
669 li r0,__got2_entries@sectoff@l
670 la r3,GOT(_GOT2_TABLE_)
671 lwz r11,GOT(_GOT2_TABLE_)
681 * Now adjust the fixups and the pointers to the fixups
682 * in case we need to move ourselves again.
684 2: li r0,__fixup_entries@sectoff@l
685 lwz r3,GOT(_FIXUP_TABLE_)
699 * Now clear BSS segment
701 lwz r3,GOT(__bss_start)
715 mr r3, r9 /* Global Data pointer */
716 mr r4, r10 /* Destination Address */
720 * Copy exception vector code to low memory
723 * r7: source address, r8: end address, r9: target address
728 lwz r8, GOT(_end_of_vectors)
730 li r9, 0x100 /* reset vector always at 0x100 */
733 bgelr /* return if r7>=r8 - just in case */
735 mflr r4 /* save link register */
745 * relocate `hdlr' and `int_return' entries
747 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
748 li r8, Alignment - _start + EXC_OFF_SYS_RESET
751 addi r7, r7, 0x100 /* next exception vector */
755 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
758 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
761 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
762 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
765 addi r7, r7, 0x100 /* next exception vector */
769 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
770 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
773 addi r7, r7, 0x100 /* next exception vector */
777 mfmsr r3 /* now that the vectors have */
778 lis r7, MSR_IP@h /* relocated into low memory */
779 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
780 andc r3, r3, r7 /* (if it was on) */
781 SYNC /* Some chip revs need this... */
785 mtlr r4 /* restore link register */
789 * Function: relocate entries for one exception vector
792 lwz r0, 0(r7) /* hdlr ... */
793 add r0, r0, r3 /* ... += dest_addr */
796 lwz r0, 4(r7) /* int_return ... */
797 add r0, r0, r3 /* ... += dest_addr */