3 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
5 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #if defined(CONFIG_HARD_I2C)
31 #include <asm/cpm_8260.h>
34 /* define to enable debug messages */
37 DECLARE_GLOBAL_DATA_PTR;
39 #if defined(CONFIG_I2C_MULTI_BUS)
40 static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0;
41 #endif /* CONFIG_I2C_MULTI_BUS */
43 /* uSec to wait between polls of the i2c */
45 /* uSec to wait for the CPM to start processing the buffer */
46 #define START_DELAY_US 1000
49 * tx/rx per-byte timeout: we delay DELAY_US uSec between polls so the
50 * timeout will be (tx_length + rx_length) * DELAY_US * TOUT_LOOP
54 /*-----------------------------------------------------------------------
57 #ifndef CONFIG_SYS_I2C_SPEED
58 #define CONFIG_SYS_I2C_SPEED 50000
61 #ifndef CONFIG_SYS_I2C_SLAVE
62 #define CONFIG_SYS_I2C_SLAVE 0xFE
64 /*-----------------------------------------------------------------------
67 typedef void (*i2c_ecb_t)(int, int, void *); /* error callback function */
69 /* This structure keeps track of the bd and buffer space usage. */
70 typedef struct i2c_state {
71 int rx_idx; /* index to next free Rx BD */
72 int tx_idx; /* index to next free Tx BD */
73 void *rxbd; /* pointer to next free Rx BD */
74 void *txbd; /* pointer to next free Tx BD */
75 int tx_space; /* number of Tx bytes left */
76 unsigned char *tx_buf; /* pointer to free Tx area */
77 i2c_ecb_t err_cb; /* error callback function */
78 void *cb_data; /* private data to be passed */
81 /* flags for i2c_send() and i2c_receive() */
82 #define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
83 #define I2CF_START_COND 0x02 /* tx: generate start condition */
84 #define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
87 #define I2CERR_NO_BUFFERS 1 /* no more BDs or buffer space */
88 #define I2CERR_MSG_TOO_LONG 2 /* tried to send/receive to much data */
89 #define I2CERR_TIMEOUT 3 /* timeout in i2c_doio() */
90 #define I2CERR_QUEUE_EMPTY 4 /* i2c_doio called without send/receive */
91 #define I2CERR_IO_ERROR 5 /* had an error during comms */
93 /* error callback flags */
94 #define I2CECB_RX_ERR 0x10 /* this is a receive error */
95 #define I2CECB_RX_OV 0x02 /* receive overrun error */
96 #define I2CECB_RX_MASK 0x0f /* mask for error bits */
97 #define I2CECB_TX_ERR 0x20 /* this is a transmit error */
98 #define I2CECB_TX_CL 0x01 /* transmit collision error */
99 #define I2CECB_TX_UN 0x02 /* transmit underflow error */
100 #define I2CECB_TX_NAK 0x04 /* transmit no ack error */
101 #define I2CECB_TX_MASK 0x0f /* mask for error bits */
102 #define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
104 #define ERROR_I2C_NONE 0
105 #define ERROR_I2C_LENGTH 1
107 #define I2C_WRITE_BIT 0x00
108 #define I2C_READ_BIT 0x01
110 #define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
115 #define MAX_TX_SPACE 256
117 typedef struct I2C_BD
119 unsigned short status;
120 unsigned short length;
123 #define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
125 #define BD_I2C_TX_CL 0x0001 /* collision error */
126 #define BD_I2C_TX_UN 0x0002 /* underflow error */
127 #define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */
128 #define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
130 #define BD_I2C_RX_ERR BD_SC_OV
133 #define PRINTD(x) printf x
139 * Returns the best value of I2BRG to meet desired clock speed of I2C with
140 * input parameters (clock speed, filter, and predivider value).
141 * It returns computer speed value and the difference between it and desired
145 i2c_roundrate(int hz, int speed, int filter, int modval,
146 int *brgval, int *totspeed)
148 int moddiv = 1 << (5-(modval & 3)), brgdiv, div;
150 PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
151 hz, speed, filter, modval));
153 div = moddiv * speed;
154 brgdiv = (hz + div - 1) / div;
156 PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv));
158 *brgval = ((brgdiv + 1) / 2) - 3 - (2*filter);
160 if ((*brgval < 0) || (*brgval > 255)) {
161 PRINTD(("\t\trejected brgval=%d\n", *brgval));
165 brgdiv = 2 * (*brgval + 3 + (2 * filter));
166 div = moddiv * brgdiv ;
167 *totspeed = hz / div;
169 PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed));
175 * Sets the I2C clock predivider and divider to meet required clock speed.
177 static int i2c_setrate(int hz, int speed)
179 immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
180 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
183 bestspeed_diff = speed,
188 filter = 0; /* Use this fixed value */
190 for (modval = 0; modval < 4; modval++)
192 if (i2c_roundrate (hz, speed, filter, modval, &brgval, &totspeed) == 0)
194 int diff = speed - totspeed ;
196 if ((diff >= 0) && (diff < bestspeed_diff))
198 bestspeed_diff = diff ;
199 bestspeed_modval = modval;
200 bestspeed_brgval = brgval;
201 bestspeed_filter = filter;
206 PRINTD(("[I2C] Best is:\n"));
207 PRINTD(("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
209 bestspeed_filter, bestspeed_modval, bestspeed_brgval,
212 i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
213 i2c->i2c_i2brg = bestspeed_brgval & 0xff;
215 PRINTD(("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod, i2c->i2c_i2brg));
220 void i2c_init(int speed, int slaveadd)
222 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
223 volatile cpm8260_t *cp = (cpm8260_t *)&immap->im_cpm;
224 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
227 volatile I2C_BD *rxbd, *txbd;
230 #ifdef CONFIG_SYS_I2C_INIT_BOARD
231 /* call board specific i2c bus reset routine before accessing the */
232 /* environment, which might be in a chip on that bus. For details */
233 /* about this problem see doc/I2C_Edge_Conditions. */
237 dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
239 /* need to allocate dual port ram */
240 dpaddr = m8260_cpm_dpalloc(64 +
241 (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) +
243 *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE])) = dpaddr;
247 * initialise data in dual port ram:
249 * dpaddr -> parameter ram (64 bytes)
250 * rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
251 * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
252 * tx buffer (MAX_TX_SPACE bytes)
255 iip = (iic_t *)&immap->im_dprambase[dpaddr];
256 memset((void*)iip, 0, sizeof(iic_t));
259 tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
261 /* Disable interrupts */
262 i2c->i2c_i2mod = 0x00;
263 i2c->i2c_i2cmr = 0x00;
264 i2c->i2c_i2cer = 0xff;
265 i2c->i2c_i2add = slaveadd;
268 * Set the I2C BRG Clock division factor from desired i2c rate
269 * and current CPU rate (we assume sccr dfbgr field is 0;
270 * divide BRGCLK by 1)
272 PRINTD(("[I2C] Setting rate...\n"));
273 i2c_setrate (gd->brg_clk, CONFIG_SYS_I2C_SPEED) ;
275 /* Set I2C controller in master mode */
276 i2c->i2c_i2com = 0x01;
278 /* Initialize Tx/Rx parameters */
279 iip->iic_rbase = rbase;
280 iip->iic_tbase = tbase;
281 rxbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_rbase]);
282 txbd = (I2C_BD *)((unsigned char *)&immap->im_dprambase[iip->iic_tbase]);
284 PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase));
285 PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase));
286 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
287 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
289 /* Set big endian byte order */
290 iip->iic_tfcr = 0x10;
291 iip->iic_rfcr = 0x10;
293 /* Set maximum receive size. */
294 iip->iic_mrblr = I2C_RXTX_LEN;
296 cp->cp_cpcr = mk_cr_cmd(CPM_CR_I2C_PAGE,
299 CPM_CR_INIT_TRX) | CPM_CR_FLG;
301 __asm__ __volatile__ ("eieio");
302 } while (cp->cp_cpcr & CPM_CR_FLG);
304 /* Clear events and interrupts */
305 i2c->i2c_i2cer = 0xff;
306 i2c->i2c_i2cmr = 0x00;
310 void i2c_newio(i2c_state_t *state)
312 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
316 PRINTD(("[I2C] i2c_newio\n"));
318 dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
319 iip = (iic_t *)&immap->im_dprambase[dpaddr];
322 state->rxbd = (void*)&immap->im_dprambase[iip->iic_rbase];
323 state->txbd = (void*)&immap->im_dprambase[iip->iic_tbase];
324 state->tx_space = MAX_TX_SPACE;
325 state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
326 state->err_cb = NULL;
327 state->cb_data = NULL;
329 PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd));
330 PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd));
331 PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf));
333 /* clear the buffer memory */
334 memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
338 int i2c_send(i2c_state_t *state,
339 unsigned char address,
340 unsigned char secondary_address,
343 unsigned char *dataout)
345 volatile I2C_BD *txbd;
348 PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
349 address, secondary_address, flags, size));
351 /* trying to send message larger than BD */
352 if (size > I2C_RXTX_LEN)
353 return I2CERR_MSG_TOO_LONG;
355 /* no more free bds */
356 if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
357 return I2CERR_NO_BUFFERS;
359 txbd = (I2C_BD *)state->txbd;
360 txbd->addr = state->tx_buf;
362 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
364 if (flags & I2CF_START_COND)
366 PRINTD(("[I2C] Formatting addresses...\n"));
367 if (flags & I2CF_ENABLE_SECONDARY)
369 txbd->length = size + 2; /* Length of message plus dest addresses */
370 txbd->addr[0] = address << 1;
371 txbd->addr[1] = secondary_address;
376 txbd->length = size + 1; /* Length of message plus dest address */
377 txbd->addr[0] = address << 1; /* Write destination address to BD */
383 txbd->length = size; /* Length of message */
388 txbd->status = BD_SC_READY;
389 if (flags & I2CF_START_COND)
390 txbd->status |= BD_I2C_TX_START;
391 if (flags & I2CF_STOP_COND)
392 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
394 /* Copy data to send into buffer */
395 PRINTD(("[I2C] copy data...\n"));
396 for(j = 0; j < size; i++, j++)
397 txbd->addr[i] = dataout[j];
399 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
406 state->tx_buf += txbd->length;
407 state->tx_space -= txbd->length;
409 state->txbd = (void*)(txbd + 1);
415 int i2c_receive(i2c_state_t *state,
416 unsigned char address,
417 unsigned char secondary_address,
419 unsigned short size_to_expect,
420 unsigned char *datain)
422 volatile I2C_BD *rxbd, *txbd;
424 PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags));
426 /* Expected to receive too much */
427 if (size_to_expect > I2C_RXTX_LEN)
428 return I2CERR_MSG_TOO_LONG;
430 /* no more free bds */
431 if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
432 || state->tx_space < 2)
433 return I2CERR_NO_BUFFERS;
435 rxbd = (I2C_BD *)state->rxbd;
436 txbd = (I2C_BD *)state->txbd;
438 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
439 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
441 txbd->addr = state->tx_buf;
443 /* set up TXBD for destination address */
444 if (flags & I2CF_ENABLE_SECONDARY)
447 txbd->addr[0] = address << 1; /* Write data */
448 txbd->addr[1] = secondary_address; /* Internal address */
449 txbd->status = BD_SC_READY;
453 txbd->length = 1 + size_to_expect;
454 txbd->addr[0] = (address << 1) | 0x01;
455 txbd->status = BD_SC_READY;
456 memset(&txbd->addr[1], 0, txbd->length);
459 /* set up rxbd for reception */
460 rxbd->status = BD_SC_EMPTY;
461 rxbd->length = size_to_expect;
464 txbd->status |= BD_I2C_TX_START;
465 if (flags & I2CF_STOP_COND)
467 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
468 rxbd->status |= BD_SC_WRAP;
471 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
476 PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
483 state->tx_buf += txbd->length;
484 state->tx_space -= txbd->length;
486 state->txbd = (void*)(txbd + 1);
488 state->rxbd = (void*)(rxbd + 1);
495 int i2c_doio(i2c_state_t *state)
497 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
499 volatile i2c8260_t *i2c = (i2c8260_t *)&immap->im_i2c;
500 volatile I2C_BD *txbd, *rxbd;
501 int n, i, b, rxcnt = 0, rxtimeo = 0, txcnt = 0, txtimeo = 0, rc = 0;
504 PRINTD(("[I2C] i2c_doio\n"));
506 if (state->tx_idx <= 0 && state->rx_idx <= 0) {
507 PRINTD(("[I2C] No I/O is queued\n"));
508 return I2CERR_QUEUE_EMPTY;
511 dpaddr = *((unsigned short*)(&immap->im_dprambase[PROFF_I2C_BASE]));
512 iip = (iic_t *)&immap->im_dprambase[dpaddr];
513 iip->iic_rbptr = iip->iic_rbase;
514 iip->iic_tbptr = iip->iic_tbase;
517 PRINTD(("[I2C] Enabling I2C...\n"));
518 i2c->i2c_i2mod |= 0x01;
520 /* Begin transmission */
521 i2c->i2c_i2com |= 0x80;
523 /* Loop until transmit & receive completed */
525 if ((n = state->tx_idx) > 0) {
527 txbd = ((I2C_BD*)state->txbd) - n;
528 for (i = 0; i < n; i++) {
529 txtimeo += TOUT_LOOP * txbd->length;
533 txbd--; /* wait until last in list is done */
535 PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd));
537 udelay(START_DELAY_US); /* give it time to start */
538 while((txbd->status & BD_SC_READY) && (++txcnt < txtimeo)) {
542 __asm__ __volatile__ ("eieio");
546 if (txcnt < txtimeo && (n = state->rx_idx) > 0) {
548 rxbd = ((I2C_BD*)state->rxbd) - n;
549 for (i = 0; i < n; i++) {
550 rxtimeo += TOUT_LOOP * rxbd->length;
554 rxbd--; /* wait until last in list is done */
556 PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd));
558 udelay(START_DELAY_US); /* give it time to start */
559 while((rxbd->status & BD_SC_EMPTY) && (++rxcnt < rxtimeo)) {
563 __asm__ __volatile__ ("eieio");
568 i2c->i2c_i2mod &= ~0x01;
570 if ((n = state->tx_idx) > 0) {
571 for (i = 0; i < n; i++) {
572 txbd = ((I2C_BD*)state->txbd) - (n - i);
573 if ((b = txbd->status & BD_I2C_TX_ERR) != 0) {
574 if (state->err_cb != NULL)
575 (*state->err_cb)(I2CECB_TX_ERR|b, i,
578 rc = I2CERR_IO_ERROR;
583 if ((n = state->rx_idx) > 0) {
584 for (i = 0; i < n; i++) {
585 rxbd = ((I2C_BD*)state->rxbd) - (n - i);
586 if ((b = rxbd->status & BD_I2C_RX_ERR) != 0) {
587 if (state->err_cb != NULL)
588 (*state->err_cb)(I2CECB_RX_ERR|b, i,
591 rc = I2CERR_IO_ERROR;
596 if ((txtimeo > 0 && txcnt >= txtimeo) || \
597 (rxtimeo > 0 && rxcnt >= rxtimeo)) {
598 if (state->err_cb != NULL)
599 (*state->err_cb)(I2CECB_TIMEOUT, -1, state->cb_data);
608 i2c_probe_callback(int flags, int xnum, void *data)
611 * the only acceptable errors are a transmit NAK or a receive
612 * overrun - tx NAK means the device does not exist, rx OV
613 * means the device must have responded to the slave address
614 * even though the transfer failed
616 if (flags == (I2CECB_TX_ERR|I2CECB_TX_NAK))
618 if (flags == (I2CECB_RX_ERR|I2CECB_RX_OV))
623 i2c_probe(uchar chip)
631 state.err_cb = i2c_probe_callback;
632 state.cb_data = (void *) &err_flag;
635 rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf);
638 return (rc); /* probe failed */
640 rc = i2c_doio(&state);
643 return (0); /* device exists - read succeeded */
645 if (rc == I2CERR_TIMEOUT)
646 return (-1); /* device does not exist - timeout */
648 if (rc != I2CERR_IO_ERROR || err_flag == 0)
649 return (rc); /* probe failed */
652 return (-1); /* device does not exist - had transmit NAK */
654 return (0); /* device exists - had receive overrun */
659 i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
665 xaddr[0] = (addr >> 24) & 0xFF;
666 xaddr[1] = (addr >> 16) & 0xFF;
667 xaddr[2] = (addr >> 8) & 0xFF;
668 xaddr[3] = addr & 0xFF;
670 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
672 * EEPROM chips that implement "address overflow" are ones
673 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
674 * and the extra bits end up in the "chip address" bit slots.
675 * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
678 * Note that we consider the length of the address field to still
679 * be one byte because the extra address bits are hidden in the
682 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
687 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
689 printf("i2c_read: i2c_send failed (%d)\n", rc);
693 rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
695 printf("i2c_read: i2c_receive failed (%d)\n", rc);
699 rc = i2c_doio(&state);
701 printf("i2c_read: i2c_doio failed (%d)\n", rc);
708 i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
714 xaddr[0] = (addr >> 24) & 0xFF;
715 xaddr[1] = (addr >> 16) & 0xFF;
716 xaddr[2] = (addr >> 8) & 0xFF;
717 xaddr[3] = addr & 0xFF;
719 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
721 * EEPROM chips that implement "address overflow" are ones
722 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of address
723 * and the extra bits end up in the "chip address" bit slots.
724 * This makes a 24WC08 (1Kbyte) chip look like four 256 byte
727 * Note that we consider the length of the address field to still
728 * be one byte because the extra address bits are hidden in the
731 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
736 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
738 printf("i2c_write: first i2c_send failed (%d)\n", rc);
742 rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
744 printf("i2c_write: second i2c_send failed (%d)\n", rc);
748 rc = i2c_doio(&state);
750 printf("i2c_write: i2c_doio failed (%d)\n", rc);
756 #if defined(CONFIG_I2C_MULTI_BUS)
758 * Functions for multiple I2C bus handling
760 unsigned int i2c_get_bus_num(void)
765 int i2c_set_bus_num(unsigned int bus)
767 #if defined(CONFIG_I2C_MUX)
768 if (bus < CONFIG_SYS_MAX_I2C_BUS) {
773 ret = i2x_mux_select_mux(bus);
780 if (bus >= CONFIG_SYS_MAX_I2C_BUS)
786 /* TODO: add 100/400k switching */
787 unsigned int i2c_get_bus_speed(void)
789 return CONFIG_SYS_I2C_SPEED;
792 int i2c_set_bus_speed(unsigned int speed)
794 if (speed != CONFIG_SYS_I2C_SPEED)
800 #endif /* CONFIG_I2C_MULTI_BUS */
801 #endif /* CONFIG_HARD_I2C */