3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/m8260_pci.h>
32 * Local->PCI map (from CPU) controlled by
33 * MPC826x master window
35 * 0x80000000 - 0xBFFFFFFF Total CPU2PCI space PCIBR0
37 * 0x80000000 - 0x8FFFFFFF PCI Mem with prefetch (Outbound ATU #1)
38 * 0x90000000 - 0x9FFFFFFF PCI Mem w/o prefetch (Outbound ATU #2)
39 * 0xA0000000 - 0xAFFFFFFF 32-bit PCI IO (Outbound ATU #3)
41 * PCI->Local map (from PCI)
42 * MPC826x slave window controlled by
44 * 0x00000000 - 0x07FFFFFF MPC826x local memory (Inbound ATU #1)
48 * Slave window that allows PCI masters to access MPC826x local memory.
49 * This window is set up using the first set of Inbound ATU registers
52 #define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
53 #define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
54 #define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
58 * This is the window that allows the CPU to access PCI address space.
59 * It will be setup with the SIU PCIBR0 register. All three PCI master
60 * windows, which allow the CPU to access PCI prefetch, non prefetch,
61 * and IO space (see below), must all fit within this window.
64 #define PCI_MSTR_LOCAL 0x80000000 /* Local base */
65 #define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
68 * Master window that allows the CPU to access PCI Memory (prefetch).
69 * This window will be setup with the first set of Outbound ATU registers
73 #define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
74 #define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
75 #define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
76 #define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
77 #define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
80 * Master window that allows the CPU to access PCI Memory (non-prefetch).
81 * This window will be setup with the second set of Outbound ATU registers
85 #define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
86 #define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
87 #define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
88 #define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256MB */
89 #define POCMR1_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE)
92 * Master window that allows the CPU to access PCI IO space.
93 * This window will be setup with the third set of Outbound ATU registers
97 #define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
99 #define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
101 #define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
103 #define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
104 #define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
105 #define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
107 /* PCI bus configuration registers.
110 #define PCI_CLASS_BRIDGE_CTLR 0x06
113 static inline void pci_outl(u32 addr, u32 data)
115 *(volatile u32 *) addr = cpu_to_le32(data);
118 void pci_mpc8250_init(struct pci_controller *hose)
121 u32 immr_addr = CFG_IMMR;
122 volatile immap_t *immap = (immap_t *) CFG_IMMR;
123 pci_dev_t host_devno = PCI_BDF(0, 0, 0);
125 pci_setup_indirect(hose, CFG_IMMR + PCI_CFG_ADDR_REG,
126 CFG_IMMR + PCI_CFG_DATA_REG);
129 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
130 * and local bus for PCI (SIUMCR [LBPC]).
132 immap->im_siu_conf.sc_siumcr = 0x00640000;
134 /* Make PCI lowest priority */
135 /* Each 4 bits is a device bus request and the MS 4bits
136 is highest priority */
146 External Master 1 0b0111
147 External Master 2 0b1000
148 External Master 3 0b1001
149 The rest are reserved */
150 immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
152 /* Park bus on core while modifying PCI Bus accesses */
153 immap->im_siu_conf.sc_ppc_acr = 0x6;
156 * Set up master window that allows the CPU to access PCI space. This
157 * window is set up using the first SIU PCIBR registers.
159 *(volatile unsigned long*)(immr_addr + M8265_PCIMSK0) = PCIMSK0_MASK;
160 *(volatile unsigned long*)(immr_addr + M8265_PCIBR0) =
161 PCI_MSTR_LOCAL | PCIBR_ENABLE;
163 /* Release PCI RST (by default the PCI RST signal is held low) */
164 pci_outl (immr_addr | PCI_GCR_REG, PCIGCR_PCI_BUS_EN);
166 /* give it some time */
170 * Set up master window that allows the CPU to access PCI Memory (prefetch)
171 * space. This window is set up using the first set of Outbound ATU registers.
173 pci_outl (immr_addr | POTAR_REG0, PCI_MSTR_MEM_BUS >> 12); /* PCI base */
174 pci_outl (immr_addr | POBAR_REG0, PCI_MSTR_MEM_LOCAL >> 12); /* Local base */
175 pci_outl (immr_addr | POCMR_REG0, POCMR0_MASK_ATTRIB); /* Size & attribute */
178 * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
179 * space. This window is set up using the second set of Outbound ATU registers.
181 pci_outl (immr_addr | POTAR_REG1, PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */
182 pci_outl (immr_addr | POBAR_REG1, PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */
183 pci_outl (immr_addr | POCMR_REG1, POCMR1_MASK_ATTRIB); /* Size & attribute */
186 * Set up master window that allows the CPU to access PCI IO space. This window
187 * is set up using the third set of Outbound ATU registers.
189 pci_outl (immr_addr | POTAR_REG2, PCI_MSTR_IO_BUS >> 12); /* PCI base */
190 pci_outl (immr_addr | POBAR_REG2, PCI_MSTR_IO_LOCAL >> 12); /* Local base */
191 pci_outl (immr_addr | POCMR_REG2, POCMR2_MASK_ATTRIB); /* Size & attribute */
194 * Set up slave window that allows PCI masters to access MPC826x local memory.
195 * This window is set up using the first set of Inbound ATU registers
197 pci_outl (immr_addr | PITAR_REG0, PCI_SLV_MEM_LOCAL >> 12); /* Local base */
198 pci_outl (immr_addr | PIBAR_REG0, PCI_SLV_MEM_BUS >> 12); /* PCI base */
199 pci_outl (immr_addr | PICMR_REG0, PICMR0_MASK_ATTRIB); /* Size & attribute */
201 /* See above for description - puts PCI request as highest priority */
202 immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
204 /* Park the bus on the PCI */
205 immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
207 /* Host mode - specify the bridge as a host-PCI bridge */
209 pci_hose_write_config_byte(hose, host_devno, PCI_CLASS_CODE,
210 PCI_CLASS_BRIDGE_CTLR);
212 /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
213 pci_hose_read_config_word(hose, host_devno, PCI_COMMAND, &tempShort);
214 pci_hose_write_config_word(hose, host_devno, PCI_COMMAND,
215 tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
217 hose->first_busno = 0;
218 hose->last_busno = 0xff;
220 /* System memory space */
221 pci_set_region(hose->regions + 0,
225 PCI_REGION_MEM | PCI_REGION_MEMORY);
227 /* PCI memory space */
228 pci_set_region(hose->regions + 1,
235 pci_set_region(hose->regions + 2,
241 hose->region_count = 3;
243 pci_register_hose(hose);
245 hose->last_busno = pci_hose_scan(hose);
248 #endif /* CONFIG_PCI */