2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
33 #include <asm/processor.h>
34 #if defined(CONFIG_OF_FLAT_TREE)
36 #elif defined(CONFIG_OF_LIBFDT)
38 #include <fdt_support.h>
41 DECLARE_GLOBAL_DATA_PTR;
45 volatile immap_t *immr;
46 ulong clock = gd->cpu_clk;
51 immr = (immap_t *)CFG_IMMR;
55 switch (pvr & 0xffff0000) {
73 printf("Unknown core, ");
76 spridr = immr->sysconf.spridr;
88 case SPR_8347E_REV10_TBGA:
89 case SPR_8347E_REV11_TBGA:
90 case SPR_8347E_REV31_TBGA:
91 case SPR_8347E_REV10_PBGA:
92 case SPR_8347E_REV11_PBGA:
93 case SPR_8347E_REV31_PBGA:
96 case SPR_8347_REV10_TBGA:
97 case SPR_8347_REV11_TBGA:
98 case SPR_8347_REV31_TBGA:
99 case SPR_8347_REV10_PBGA:
100 case SPR_8347_REV11_PBGA:
101 case SPR_8347_REV31_PBGA:
104 case SPR_8343E_REV10:
105 case SPR_8343E_REV11:
106 case SPR_8343E_REV31:
114 case SPR_8360E_REV10:
115 case SPR_8360E_REV11:
116 case SPR_8360E_REV12:
117 case SPR_8360E_REV20:
118 case SPR_8360E_REV21:
128 case SPR_8323E_REV10:
129 case SPR_8323E_REV11:
136 case SPR_8321E_REV10:
137 case SPR_8321E_REV11:
147 case SPR_8311E_REV10:
153 case SPR_8313E_REV10:
156 case SPR_8379E_REV10:
162 case SPR_8378E_REV10:
168 case SPR_8377E_REV10:
175 printf("Rev: Unknown revision number:%08x\n"
176 "Warning: Unsupported cpu revision!\n",spridr);
180 #if defined(CONFIG_MPC834X)
181 /* Multiple revisons of 834x processors may have the same SPRIDR value.
182 * So use PVR to identify the revision number.
184 printf("Rev: %02x at %s MHz", PVR_MAJ(pvr)<<4 | PVR_MIN(pvr), strmhz(buf, clock));
186 printf("Rev: %02x at %s MHz", spridr & 0x0000FFFF, strmhz(buf, clock));
188 printf(", CSB: %4d MHz\n", gd->csb_clk / 1000000);
195 * Program a UPM with the code supplied in the table.
197 * The 'dummy' variable is used to increment the MAD. 'dummy' is
198 * supposed to be a pointer to the memory of the device being
199 * programmed by the UPM. The data in the MDR is written into
200 * memory and the MAD is incremented every time there's a read
201 * from 'dummy'. Unfortunately, the current prototype for this
202 * function doesn't allow for passing the address of this
203 * device, and changing the prototype will break a number lots
204 * of other code, so we need to use a round-about way of finding
205 * the value for 'dummy'.
207 * The value can be extracted from the base address bits of the
208 * Base Register (BR) associated with the specific UPM. To find
209 * that BR, we need to scan all 8 BRs until we find the one that
210 * has its MSEL bits matching the UPM we want. Once we know the
211 * right BR, we can extract the base address bits from it.
213 * The MxMR and the BR and OR of the chosen bank should all be
214 * configured before calling this function.
217 * upm: 0=UPMA, 1=UPMB, 2=UPMC
218 * table: Pointer to an array of values to program
219 * size: Number of elements in the array. Must be 64 or less.
221 void upmconfig (uint upm, uint *table, uint size)
223 #if defined(CONFIG_MPC834X)
224 volatile immap_t *immap = (immap_t *) CFG_IMMR;
225 volatile lbus83xx_t *lbus = &immap->lbus;
226 volatile uchar *dummy = NULL;
227 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
228 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
231 /* Scan all the banks to determine the base address of the device */
232 for (i = 0; i < 8; i++) {
233 if ((lbus->bank[i].br & BR_MSEL) == msel) {
234 dummy = (uchar *) (lbus->bank[i].br & BR_BA);
240 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
244 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
245 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
247 for (i = 0; i < size; i++) {
248 lbus->mdr = table[i];
249 __asm__ __volatile__ ("sync");
250 *dummy; /* Write the value to memory and increment MAD */
251 __asm__ __volatile__ ("sync");
254 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
257 printf("Error: %s() not defined for this configuration.\n", __FUNCTION__);
264 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
267 #ifndef MPC83xx_RESET
271 volatile immap_t *immap = (immap_t *) CFG_IMMR;
274 /* Interrupts and MMU off */
275 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
277 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
278 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
280 /* enable Reset Control Reg */
281 immap->reset.rpr = 0x52535445;
282 __asm__ __volatile__ ("sync");
283 __asm__ __volatile__ ("isync");
285 /* confirm Reset Control Reg is enabled */
286 while(!((immap->reset.rcer) & RCER_CRE));
288 printf("Resetting the board.");
293 /* perform reset, only one bit */
294 immap->reset.rcr = RCR_SWHR;
296 #else /* ! MPC83xx_RESET */
298 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
300 /* Interrupts and MMU off */
301 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
303 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
304 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
307 * Trying to execute the next instruction at a non-existing address
308 * should cause a machine check, resulting in reset
310 addr = CFG_RESET_ADDRESS;
312 printf("resetting the board.");
314 ((void (*)(void)) addr) ();
315 #endif /* MPC83xx_RESET */
322 * Get timebase clock frequency (like cpu_clk in Hz)
325 unsigned long get_tbclk(void)
329 tbclk = (gd->bus_clk + 3L) / 4L;
335 #if defined(CONFIG_WATCHDOG)
336 void watchdog_reset (void)
338 int re_enable = disable_interrupts();
340 /* Reset the 83xx watchdog */
341 volatile immap_t *immr = (immap_t *) CFG_IMMR;
342 immr->wdt.swsrr = 0x556c;
343 immr->wdt.swsrr = 0xaa39;
346 enable_interrupts ();
350 #if defined(CONFIG_OF_LIBFDT)
353 * "Setter" functions used to add/modify FDT entries.
355 static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd)
357 /* Fix it up if it exists, don't create it if it doesn't exist */
358 if (fdt_get_property(blob, nodeoffset, name, 0)) {
359 return fdt_setprop(blob, nodeoffset, name, bd->bi_enetaddr, 6);
363 #ifdef CONFIG_HAS_ETH1
364 /* second onboard ethernet port */
365 static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd)
367 /* Fix it up if it exists, don't create it if it doesn't exist */
368 if (fdt_get_property(blob, nodeoffset, name, 0)) {
369 return fdt_setprop(blob, nodeoffset, name, bd->bi_enet1addr, 6);
374 #ifdef CONFIG_HAS_ETH2
375 /* third onboard ethernet port */
376 static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd)
378 /* Fix it up if it exists, don't create it if it doesn't exist */
379 if (fdt_get_property(blob, nodeoffset, name, 0)) {
380 return fdt_setprop(blob, nodeoffset, name, bd->bi_enet2addr, 6);
385 #ifdef CONFIG_HAS_ETH3
386 /* fourth onboard ethernet port */
387 static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd)
389 /* Fix it up if it exists, don't create it if it doesn't exist */
390 if (fdt_get_property(blob, nodeoffset, name, 0)) {
391 return fdt_setprop(blob, nodeoffset, name, bd->bi_enet3addr, 6);
397 static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
400 /* Create or update the property */
401 tmp = cpu_to_be32(bd->bi_busfreq);
402 return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
405 static int fdt_set_tbfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
408 /* Create or update the property */
409 tmp = cpu_to_be32(OF_TBCLK);
410 return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
414 static int fdt_set_clockfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
417 /* Create or update the property */
418 tmp = cpu_to_be32(gd->core_clk);
419 return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
423 static int fdt_set_qe_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
426 /* Create or update the property */
427 tmp = cpu_to_be32(gd->qe_clk);
428 return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
431 static int fdt_set_qe_brgfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
434 /* Create or update the property */
435 tmp = cpu_to_be32(gd->brg_clk);
436 return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
443 static const struct {
446 int (*set_fn)(void *blob, int nodeoffset, const char *name, bd_t *bd);
449 "timebase-frequency",
464 { "/" OF_SOC "/serial@4500",
468 { "/" OF_SOC "/serial@4600",
473 { "/" OF_SOC "/ethernet@24000",
477 { "/" OF_SOC "/ethernet@24000",
483 { "/" OF_SOC "/ethernet@25000",
487 { "/" OF_SOC "/ethernet@25000",
501 #ifdef CONFIG_UEC_ETH1
502 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
503 { "/" OF_QE "/ucc@2000",
507 { "/" OF_QE "/ucc@2000",
511 #elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
512 { "/" OF_QE "/ucc@2200",
516 { "/" OF_QE "/ucc@2200",
521 #endif /* CONFIG_UEC_ETH1 */
522 #ifdef CONFIG_UEC_ETH2
523 #if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
524 { "/" OF_QE "/ucc@3000",
528 { "/" OF_QE "/ucc@3000",
532 #elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */
533 { "/" OF_QE "/ucc@3200",
537 { "/" OF_QE "/ucc@3200",
542 #endif /* CONFIG_UEC_ETH2 */
543 #endif /* CONFIG_QE */
547 ft_cpu_setup(void *blob, bd_t *bd)
553 for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
554 nodeoffset = fdt_path_offset(blob, fixup_props[j].node);
555 if (nodeoffset >= 0) {
556 err = fixup_props[j].set_fn(blob, nodeoffset,
557 fixup_props[j].prop, bd);
559 debug("Problem setting %s = %s: %s\n",
560 fixup_props[j].node, fixup_props[j].prop,
563 debug("Couldn't find %s: %s\n",
564 fixup_props[j].node, fdt_strerror(nodeoffset));
568 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
570 #elif defined(CONFIG_OF_FLAT_TREE)
572 ft_cpu_setup(void *blob, bd_t *bd)
578 clock = bd->bi_busfreq;
579 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
581 *p = cpu_to_be32(clock);
583 p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
585 *p = cpu_to_be32(clock);
587 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
589 *p = cpu_to_be32(clock);
591 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
593 *p = cpu_to_be32(clock);
596 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
598 memcpy(p, bd->bi_enetaddr, 6);
600 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/local-mac-address", &len);
602 memcpy(p, bd->bi_enetaddr, 6);
606 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
608 memcpy(p, bd->bi_enet1addr, 6);
610 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/local-mac-address", &len);
612 memcpy(p, bd->bi_enet1addr, 6);
615 #ifdef CONFIG_UEC_ETH1
616 #if CFG_UEC1_UCC_NUM == 0 /* UCC1 */
617 p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
619 memcpy(p, bd->bi_enetaddr, 6);
621 p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
623 memcpy(p, bd->bi_enetaddr, 6);
624 #elif CFG_UEC1_UCC_NUM == 2 /* UCC3 */
625 p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/mac-address", &len);
627 memcpy(p, bd->bi_enetaddr, 6);
629 p = ft_get_prop(blob, "/" OF_QE "/ucc@2200/local-mac-address", &len);
631 memcpy(p, bd->bi_enetaddr, 6);
635 #ifdef CONFIG_UEC_ETH2
636 #if CFG_UEC2_UCC_NUM == 1 /* UCC2 */
637 p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
639 memcpy(p, bd->bi_enet1addr, 6);
641 p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
643 memcpy(p, bd->bi_enet1addr, 6);
644 #elif CFG_UEC2_UCC_NUM == 3 /* UCC4 */
645 p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/mac-address", &len);
647 memcpy(p, bd->bi_enet1addr, 6);
649 p = ft_get_prop(blob, "/" OF_QE "/ucc@3200/local-mac-address", &len);
651 memcpy(p, bd->bi_enet1addr, 6);
657 #if defined(CONFIG_DDR_ECC)
660 volatile immap_t *immap = (immap_t *)CFG_IMMR;
661 volatile dma83xx_t *dma = &immap->dma;
662 volatile u32 status = swab32(dma->dmasr0);
663 volatile u32 dmamr0 = swab32(dma->dmamr0);
667 /* initialize DMASARn, DMADAR and DMAABCRn */
668 dma->dmadar0 = (u32)0;
669 dma->dmasar0 = (u32)0;
672 __asm__ __volatile__ ("sync");
673 __asm__ __volatile__ ("isync");
676 dmamr0 &= ~DMA_CHANNEL_START;
677 dma->dmamr0 = swab32(dmamr0);
678 __asm__ __volatile__ ("sync");
679 __asm__ __volatile__ ("isync");
681 /* while the channel is busy, spin */
682 while(status & DMA_CHANNEL_BUSY) {
683 status = swab32(dma->dmasr0);
686 debug("DMA-init end\n");
691 volatile immap_t *immap = (immap_t *)CFG_IMMR;
692 volatile dma83xx_t *dma = &immap->dma;
693 volatile u32 status = swab32(dma->dmasr0);
694 volatile u32 byte_count = swab32(dma->dmabcr0);
696 /* while the channel is busy, spin */
697 while (status & DMA_CHANNEL_BUSY) {
698 status = swab32(dma->dmasr0);
701 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
702 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
708 int dma_xfer(void *dest, u32 count, void *src)
710 volatile immap_t *immap = (immap_t *)CFG_IMMR;
711 volatile dma83xx_t *dma = &immap->dma;
714 /* initialize DMASARn, DMADAR and DMAABCRn */
715 dma->dmadar0 = swab32((u32)dest);
716 dma->dmasar0 = swab32((u32)src);
717 dma->dmabcr0 = swab32(count);
719 __asm__ __volatile__ ("sync");
720 __asm__ __volatile__ ("isync");
722 /* init direct transfer, clear CS bit */
723 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
724 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
725 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
727 dma->dmamr0 = swab32(dmamr0);
729 __asm__ __volatile__ ("sync");
730 __asm__ __volatile__ ("isync");
732 /* set CS to start DMA transfer */
733 dmamr0 |= DMA_CHANNEL_START;
734 dma->dmamr0 = swab32(dmamr0);
735 __asm__ __volatile__ ("sync");
736 __asm__ __volatile__ ("isync");
738 return ((int)dma_check());
740 #endif /*CONFIG_DDR_ECC*/