git.sur5r.net Git - u-boot/blob - cpu/mpc83xx/cpu_init.c

   1 /*
   2  * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <mpc83xx.h>
  25 #include <ioports.h>
  26 #ifdef CONFIG_USB_EHCI_FSL
  27 #include <asm/io.h>
  28 #include <usb/ehci-fsl.h>
  29 #endif
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 #ifdef CONFIG_QE
  34 extern qe_iop_conf_t qe_iop_conf_tab[];
  35 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  36                          int open_drain, int assign);
  37 extern void qe_init(uint qe_base);
  38 extern void qe_reset(void);
  39
  40 static void config_qe_ioports(void)
  41 {
  42         u8      port, pin;
  43         int     dir, open_drain, assign;
  44         int     i;
  45
  46         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  47                 port            = qe_iop_conf_tab[i].port;
  48                 pin             = qe_iop_conf_tab[i].pin;
  49                 dir             = qe_iop_conf_tab[i].dir;
  50                 open_drain      = qe_iop_conf_tab[i].open_drain;
  51                 assign          = qe_iop_conf_tab[i].assign;
  52                 qe_config_iopin(port, pin, dir, open_drain, assign);
  53         }
  54 }
  55 #endif
  56
  57 /*
  58  * Breathe some life into the CPU...
  59  *
  60  * Set up the memory map,
  61  * initialize a bunch of registers,
  62  * initialize the UPM's
  63  */
  64 void cpu_init_f (volatile immap_t * im)
  65 {
  66         /* Pointer is writable since we allocated a register for it */
  67         gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  68
  69         /* Clear initial global data */
  70         memset ((void *) gd, 0, sizeof (gd_t));
  71
  72         /* system performance tweaking */
  73
  74 #ifdef CONFIG_SYS_ACR_PIPE_DEP
  75         /* Arbiter pipeline depth */
  76         im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
  77                           (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
  78 #endif
  79
  80 #ifdef CONFIG_SYS_ACR_RPTCNT
  81         /* Arbiter repeat count */
  82         im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
  83                           (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
  84 #endif
  85
  86 #ifdef CONFIG_SYS_SPCR_OPT
  87         /* Optimize transactions between CSB and other devices */
  88         im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
  89                            (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
  90 #endif
  91
  92 #ifdef CONFIG_SYS_SPCR_TSECEP
  93         /* all eTSEC's Emergency priority */
  94         im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) |
  95                            (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
  96 #endif
  97
  98 #ifdef CONFIG_SYS_SPCR_TSEC1EP
  99         /* TSEC1 Emergency priority */
 100         im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) |
 101                            (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
 102 #endif
 103
 104 #ifdef CONFIG_SYS_SPCR_TSEC2EP
 105         /* TSEC2 Emergency priority */
 106         im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) |
 107                            (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
 108 #endif
 109
 110 #ifdef CONFIG_SYS_SCCR_ENCCM
 111         /* Encryption clock mode */
 112         im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) |
 113                        (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT);
 114 #endif
 115
 116 #ifdef CONFIG_SYS_SCCR_PCICM
 117         /* PCI & DMA clock mode */
 118         im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) |
 119                        (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT);
 120 #endif
 121
 122 #ifdef CONFIG_SYS_SCCR_TSECCM
 123         /* all TSEC's clock mode */
 124         im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) |
 125                        (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT);
 126 #endif
 127
 128 #ifdef CONFIG_SYS_SCCR_TSEC1CM
 129         /* TSEC1 clock mode */
 130         im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) |
 131                        (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
 132 #endif
 133
 134 #ifdef CONFIG_SYS_SCCR_TSEC2CM
 135         /* TSEC2 clock mode */
 136         im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) |
 137                        (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
 138 #endif
 139
 140 #ifdef CONFIG_SYS_SCCR_TSEC1ON
 141         /* TSEC1 clock switch */
 142         im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) |
 143                        (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
 144 #endif
 145
 146 #ifdef CONFIG_SYS_SCCR_TSEC2ON
 147         /* TSEC2 clock switch */
 148         im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) |
 149                        (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
 150 #endif
 151
 152 #ifdef CONFIG_SYS_SCCR_USBMPHCM
 153         /* USB MPH clock mode */
 154         im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) |
 155                        (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
 156 #endif
 157
 158 #ifdef CONFIG_SYS_SCCR_USBDRCM
 159         /* USB DR clock mode */
 160         im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) |
 161                        (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
 162 #endif
 163
 164 #ifdef CONFIG_SYS_SCCR_SATACM
 165         /* SATA controller clock mode */
 166         im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) |
 167                        (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT);
 168 #endif
 169
 170         /* RSR - Reset Status Register - clear all status (4.6.1.3) */
 171         gd->reset_status = im->reset.rsr;
 172         im->reset.rsr = ~(RSR_RES);
 173
 174         /* AER - Arbiter Event Register - store status */
 175         gd->arbiter_event_attributes = im->arbiter.aeatr;
 176         gd->arbiter_event_address = im->arbiter.aeadr;
 177
 178         /*
 179          * RMR - Reset Mode Register
 180          * contains checkstop reset enable (4.6.1.4)
 181          */
 182         im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
 183
 184         /* LCRR - Clock Ratio Register (10.3.1.16) */
 185         im->lbus.lcrr = CONFIG_SYS_LCRR;
 186
 187         /* Enable Time Base & Decrimenter ( so we will have udelay() )*/
 188         im->sysconf.spcr |= SPCR_TBEN;
 189
 190         /* System General Purpose Register */
 191 #ifdef CONFIG_SYS_SICRH
 192 #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
 193         /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
 194         im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH;
 195 #else
 196         im->sysconf.sicrh = CONFIG_SYS_SICRH;
 197 #endif
 198 #endif
 199 #ifdef CONFIG_SYS_SICRL
 200         im->sysconf.sicrl = CONFIG_SYS_SICRL;
 201 #endif
 202         /* DDR control driver register */
 203 #ifdef CONFIG_SYS_DDRCDR
 204         im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
 205 #endif
 206         /* Output buffer impedance register */
 207 #ifdef CONFIG_SYS_OBIR
 208         im->sysconf.obir = CONFIG_SYS_OBIR;
 209 #endif
 210
 211 #ifdef CONFIG_QE
 212         /* Config QE ioports */
 213         config_qe_ioports();
 214 #endif
 215
 216         /*
 217          * Memory Controller:
 218          */
 219
 220         /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
 221          * addresses - these have to be modified later when FLASH size
 222          * has been determined
 223          */
 224
 225 #if defined(CONFIG_SYS_BR0_PRELIM)  \
 226         && defined(CONFIG_SYS_OR0_PRELIM) \
 227         && defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \
 228         && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
 229         im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM;
 230         im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM;
 231         im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
 232         im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
 233 #else
 234 #error  CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
 235 #endif
 236
 237 #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
 238         im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM;
 239         im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM;
 240 #endif
 241 #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
 242         im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
 243         im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
 244 #endif
 245 #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
 246         im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM;
 247         im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM;
 248 #endif
 249 #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
 250         im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
 251         im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
 252 #endif
 253 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
 254         im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM;
 255         im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM;
 256 #endif
 257 #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
 258         im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
 259         im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
 260 #endif
 261 #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
 262         im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM;
 263         im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM;
 264 #endif
 265 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
 266         im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
 267         im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
 268 #endif
 269 #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
 270         im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM;
 271         im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM;
 272 #endif
 273 #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
 274         im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
 275         im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
 276 #endif
 277 #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
 278         im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM;
 279         im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM;
 280 #endif
 281 #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
 282         im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
 283         im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
 284 #endif
 285 #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
 286         im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM;
 287         im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM;
 288 #endif
 289 #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
 290         im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
 291         im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
 292 #endif
 293 #ifdef CONFIG_SYS_GPIO1_PRELIM
 294         im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
 295         im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
 296 #endif
 297 #ifdef CONFIG_SYS_GPIO2_PRELIM
 298         im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
 299         im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
 300 #endif
 301 #ifdef CONFIG_USB_EHCI_FSL
 302         uint32_t temp;
 303         struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
 304
 305         /* Configure interface. */
 306         setbits_be32((void *)ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
 307
 308         /* Wait for clock to stabilize */
 309         do {
 310                 temp = in_be32((void *)ehci->control);
 311                 udelay(1000);
 312         } while (!(temp & PHY_CLK_VALID));
 313 #endif
 314 }
 315
 316 int cpu_init_r (void)
 317 {
 318 #ifdef CONFIG_QE
 319         uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
 320         qe_init(qe_base);
 321         qe_reset();
 322 #endif
 323         return 0;
 324 }
 325
 326 /*
 327  * Print out the bus arbiter event
 328  */
 329 #if defined(CONFIG_DISPLAY_AER_FULL)
 330 static int print_83xx_arb_event(int force)
 331 {
 332         static char* event[] = {
 333                 "Address Time Out",
 334                 "Data Time Out",
 335                 "Address Only Transfer Type",
 336                 "External Control Word Transfer Type",
 337                 "Reserved Transfer Type",
 338                 "Transfer Error",
 339                 "reserved",
 340                 "reserved"
 341         };
 342         static char* master[] = {
 343                 "e300 Core Data Transaction",
 344                 "reserved",
 345                 "e300 Core Instruction Fetch",
 346                 "reserved",
 347                 "TSEC1",
 348                 "TSEC2",
 349                 "USB MPH",
 350                 "USB DR",
 351                 "Encryption Core",
 352                 "I2C Boot Sequencer",
 353                 "JTAG",
 354                 "reserved",
 355                 "eSDHC",
 356                 "PCI1",
 357                 "PCI2",
 358                 "DMA",
 359                 "QUICC Engine 00",
 360                 "QUICC Engine 01",
 361                 "QUICC Engine 10",
 362                 "QUICC Engine 11",
 363                 "reserved",
 364                 "reserved",
 365                 "reserved",
 366                 "reserved",
 367                 "SATA1",
 368                 "SATA2",
 369                 "SATA3",
 370                 "SATA4",
 371                 "reserved",
 372                 "PCI Express 1",
 373                 "PCI Express 2",
 374                 "TDM-DMAC"
 375         };
 376         static char *transfer[] = {
 377                 "Address-only, Clean Block",
 378                 "Address-only, lwarx reservation set",
 379                 "Single-beat or Burst write",
 380                 "reserved",
 381                 "Address-only, Flush Block",
 382                 "reserved",
 383                 "Burst write",
 384                 "reserved",
 385                 "Address-only, sync",
 386                 "Address-only, tlbsync",
 387                 "Single-beat or Burst read",
 388                 "Single-beat or Burst read",
 389                 "Address-only, Kill Block",
 390                 "Address-only, icbi",
 391                 "Burst read",
 392                 "reserved",
 393                 "Address-only, eieio",
 394                 "reserved",
 395                 "Single-beat write",
 396                 "reserved",
 397                 "ecowx - Illegal single-beat write",
 398                 "reserved",
 399                 "reserved",
 400                 "reserved",
 401                 "Address-only, TLB Invalidate",
 402                 "reserved",
 403                 "Single-beat or Burst read",
 404                 "reserved",
 405                 "eciwx - Illegal single-beat read",
 406                 "reserved",
 407                 "Burst read",
 408                 "reserved"
 409         };
 410
 411         int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
 412                     >> AEATR_EVENT_SHIFT;
 413         int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
 414                       >> AEATR_MSTR_ID_SHIFT;
 415         int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
 416                    >> AEATR_TBST_SHIFT;
 417         int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
 418                     >> AEATR_TSIZE_SHIFT;
 419         int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
 420                     >> AEATR_TTYPE_SHIFT;
 421
 422         if (!force && !gd->arbiter_event_address)
 423                 return 0;
 424
 425         puts("Arbiter Event Status:\n");
 426         printf("       Event Address: 0x%08lX\n", gd->arbiter_event_address);
 427         printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
 428         printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
 429         printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
 430                                 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
 431         printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
 432
 433         return gd->arbiter_event_address;
 434 }
 435
 436 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
 437
 438 static int print_83xx_arb_event(int force)
 439 {
 440         if (!force && !gd->arbiter_event_address)
 441                 return 0;
 442
 443         printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
 444                 gd->arbiter_event_attributes, gd->arbiter_event_address);
 445
 446         return gd->arbiter_event_address;
 447 }
 448 #endif /* CONFIG_DISPLAY_AER_xxxx */
 449
 450 /*
 451  * Figure out the cause of the reset
 452  */
 453 int prt_83xx_rsr(void)
 454 {
 455         static struct {
 456                 ulong mask;
 457                 char *desc;
 458         } bits[] = {
 459                 {
 460                 RSR_SWSR, "Software Soft"}, {
 461                 RSR_SWHR, "Software Hard"}, {
 462                 RSR_JSRS, "JTAG Soft"}, {
 463                 RSR_CSHR, "Check Stop"}, {
 464                 RSR_SWRS, "Software Watchdog"}, {
 465                 RSR_BMRS, "Bus Monitor"}, {
 466                 RSR_SRS,  "External/Internal Soft"}, {
 467                 RSR_HRS,  "External/Internal Hard"}
 468         };
 469         static int n = sizeof bits / sizeof bits[0];
 470         ulong rsr = gd->reset_status;
 471         int i;
 472         char *sep;
 473
 474         puts("Reset Status:");
 475
 476         sep = " ";
 477         for (i = 0; i < n; i++)
 478                 if (rsr & bits[i].mask) {
 479                         printf("%s%s", sep, bits[i].desc);
 480                         sep = ", ";
 481                 }
 482         puts("\n");
 483
 484 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
 485         print_83xx_arb_event(rsr & RSR_BMRS);
 486 #endif
 487         puts("\n");
 488
 489         return 0;
 490 }