2 * (C) Copyright 2006 Freescale Semiconductor, Inc.
4 * (C) Copyright 2003,Motorola Inc.
5 * Xianghua Xiao <x.xiao@motorola.com>
6 * Adapted for Motorola 85xx chip.
9 * Gleb Natapov <gnatapov@mrv.com>
10 * Some bits are taken from linux driver writen by adrian@humboldt.co.uk
12 * Hardware I2C driver for MPC107 PCI bridge.
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 * 20050101: Eran Liberty (liberty@freescale.com)
35 * Initial file creating (porting from 85XX & 8260)
36 * 20060601: Dave Liu (daveliu@freescale.com)
37 * Unified variable names for mpc83xx
44 #ifdef CONFIG_HARD_I2C
48 DECLARE_GLOBAL_DATA_PTR;
50 /* Initialize the bus pointer to whatever one the SPD EEPROM is on.
51 * Default is bus 1. This is necessary because the DDR initialization
52 * runs from ROM, and we can't switch buses because we can't modify
53 * the i2c_dev variable. Everything gets straightened out once i2c_init
54 * is called from RAM. */
56 #ifndef CFG_SPD_BUS_NUM
57 #define CFG_SPD_BUS_NUM 1
60 static unsigned int i2c_bus_num = CFG_SPD_BUS_NUM;
62 #if CFG_SPD_BUS_NUM == 1
63 static volatile i2c_t *i2c_dev = I2C_1;
65 static volatile i2c_t *i2c_dev = I2C_2;
68 static int i2c_bus_speed[2] = {0, 0};
71 * Map the frequency divider to the FDR. This data is taken from table 17-5
72 * of the MPC8349EA reference manual, with duplicates removed.
133 #define NUM_I2C_SPEEDS (sizeof(i2c_speed_map) / sizeof(i2c_speed_map[0]))
135 static int set_speed(unsigned int speed)
137 unsigned long i2c_clk;
138 unsigned int divider, i;
141 i2c_clk = (i2c_bus_num == 2) ? gd->i2c2_clk : gd->i2c1_clk;
143 divider = i2c_clk / speed;
145 /* Scan i2c_speed_map[] for the closest matching divider.*/
147 for (i = 0; i < NUM_I2C_SPEEDS-1; i++) {
148 /* Locate our divider in between two entries in i2c_speed_map[] */
149 if ((divider >= i2c_speed_map[i].divider) &&
150 (divider <= i2c_speed_map[i+1].divider)) {
151 /* Which one is closer? */
152 if ((divider - i2c_speed_map[i].divider) < (i2c_speed_map[i+1].divider - divider)) {
153 fdr = i2c_speed_map[i].fdr;
155 fdr = i2c_speed_map[i+1].fdr;
161 writeb(fdr, &i2c_dev->fdr);
162 i2c_bus_speed[i2c_bus_num - 1] = speed;
168 static void _i2c_init(int speed, int slaveadd)
170 /* stop I2C controller */
171 writeb(0x00 , &i2c_dev->cr);
176 /* set default filter */
177 writeb(IC2_FDR,&i2c_dev->dfsrr);
179 /* write slave address */
180 writeb(slaveadd, &i2c_dev->adr);
182 /* clear status register */
183 writeb(I2C_CR_MTX, &i2c_dev->sr);
185 /* start I2C controller */
186 writeb(I2C_CR_MEN, &i2c_dev->cr);
189 void i2c_init(int speed, int slaveadd)
191 /* Set both interfaces to the same speed and slave address */
192 /* Note: This function gets called twice - before and after
193 * relocation to RAM. The first time it's called, we are unable
194 * to change buses, so whichever one 'i2c_dev' was initialized to
195 * gets set twice. When run from RAM both buses get set properly */
198 _i2c_init(speed, slaveadd);
199 #ifdef CFG_I2C2_OFFSET
201 _i2c_init(speed, slaveadd);
203 #endif /* CFG_I2C2_OFFSET */
206 static __inline__ int
209 ulong timeval = get_timer (0);
210 while (readb(&i2c_dev->sr) & I2C_SR_MBB) {
211 if (get_timer (timeval) > I2C_TIMEOUT) {
218 static __inline__ int
222 ulong timeval = get_timer(0);
224 csr = readb(&i2c_dev->sr);
226 if (!(csr & I2C_SR_MIF))
229 writeb(0x0, &i2c_dev->sr);
231 if (csr & I2C_SR_MAL) {
232 debug("i2c_wait: MAL\n");
236 if (!(csr & I2C_SR_MCF)) {
237 debug("i2c_wait: unfinished\n");
241 if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) {
242 debug("i2c_wait: No RXACK\n");
247 } while (get_timer (timeval) < I2C_TIMEOUT);
249 debug("i2c_wait: timed out\n");
253 static __inline__ int
254 i2c_write_addr (u8 dev, u8 dir, int rsta)
256 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX |
257 (rsta?I2C_CR_RSTA:0),
260 writeb((dev << 1) | dir, &i2c_dev->dr);
262 if (i2c_wait (I2C_WRITE) < 0)
267 static __inline__ int
268 __i2c_write (u8 *data, int length)
272 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
275 for (i=0; i < length; i++) {
276 writeb(data[i], &i2c_dev->dr);
278 if (i2c_wait (I2C_WRITE) < 0)
284 static __inline__ int
285 __i2c_read (u8 *data, int length)
289 writeb(I2C_CR_MEN | I2C_CR_MSTA |
290 ((length == 1) ? I2C_CR_TXAK : 0),
296 for (i=0; i < length; i++) {
297 if (i2c_wait (I2C_READ) < 0)
300 /* Generate ack on last next to last byte */
302 writeb(I2C_CR_MEN | I2C_CR_MSTA |
306 /* Generate stop on last byte */
308 writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev->cr);
310 data[i] = readb(&i2c_dev->dr);
316 i2c_read (u8 dev, uint addr, int alen, u8 *data, int length)
321 if (i2c_wait4bus () < 0)
324 if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
327 if (__i2c_write (&a[4 - alen], alen) != alen)
330 if (i2c_write_addr (dev, I2C_READ, 1) == 0)
333 i = __i2c_read (data, length);
336 writeb(I2C_CR_MEN, &i2c_dev->cr);
337 return !(i == length);
341 i2c_write (u8 dev, uint addr, int alen, u8 *data, int length)
346 if (i2c_wait4bus () < 0)
349 if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
352 if (__i2c_write (&a[4 - alen], alen) != alen)
355 i = __i2c_write (data, length);
358 writeb(I2C_CR_MEN, &i2c_dev->cr);
359 return !(i == length);
362 int i2c_probe (uchar chip)
367 * Try to read the first location of the chip. The underlying
368 * driver doesn't appear to support sending just the chip address
369 * and looking for an <ACK> back.
372 return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
375 uchar i2c_reg_read (uchar i2c_addr, uchar reg)
379 i2c_read (i2c_addr, reg, 1, buf, 1);
384 void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
386 i2c_write (i2c_addr, reg, 1, &val, 1);
389 int i2c_set_bus_num(unsigned int bus)
395 #ifdef CFG_I2C2_OFFSET
409 int i2c_set_bus_speed(unsigned int speed)
411 return set_speed(speed);
414 unsigned int i2c_get_bus_num(void)
419 unsigned int i2c_get_bus_speed(void)
421 return i2c_bus_speed[i2c_bus_num - 1];
423 #endif /* CONFIG_HARD_I2C */