2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * 20050101: Eran Liberty (liberty@freescale.com)
27 * Initial file creating (porting from 85XX & 8260)
31 #include <asm/processor.h>
35 #include <spd_sdram.h>
37 #ifdef CONFIG_SPD_EEPROM
39 #if defined(CONFIG_DDR_ECC)
40 extern void dma_init(void);
41 extern uint dma_check(void);
42 extern int dma_xfer(void *dest, uint count, void *src);
46 #define CFG_READ_SPD i2c_read
50 * Convert picoseconds into clock cycles (rounding up if needed).
54 picos_to_clk(int picos)
58 clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
59 if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
66 unsigned int banksize(unsigned char row_dens)
68 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
71 int read_spd(uint addr)
76 long int spd_sdram(int(read_spd)(uint addr))
78 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
79 volatile ddr8349_t *ddr = &immap->ddr;
80 volatile law8349_t *ecm = &immap->sysconf.ddrlaw[0];
84 unsigned int law_size;
86 unsigned int trfc, trfc_clk, trfc_low;
88 #warning Current spd_sdram does not fit its usage... adjust implementation or API...
90 CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
93 puts("DDR:Only two chip selects are supported on ADS.\n");
97 if (spd.nrow_addr < 12
100 || spd.ncol_addr > 11) {
101 puts("DDR:Row or Col number unsupported.\n");
105 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
106 ddr->cs_config[2] = ( 1 << 31
107 | (spd.nrow_addr - 12) << 8
108 | (spd.ncol_addr - 8) );
110 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
111 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
113 if (spd.nrows == 2) {
114 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
115 | ((banksize(spd.row_dens) >> 23) - 1) );
116 ddr->cs_config[3] = ( 1<<31
117 | (spd.nrow_addr-12) << 8
118 | (spd.ncol_addr-8) );
119 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
120 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
123 if (spd.mem_type != 0x07) {
124 puts("No DDR module found!\n");
129 * Figure out memory size in Megabytes.
131 memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
134 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
136 law_size = 19 + __ilog2(memsize);
139 * Set up LAWBAR for all of DDR.
141 ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
142 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
143 debug("DDR:bar=0x%08x\n", ecm->bar);
144 debug("DDR:ar=0x%08x\n", ecm->ar);
147 * find the largest CAS
149 if(spd.cas_lat & 0x40) {
151 } else if (spd.cas_lat & 0x20) {
153 } else if (spd.cas_lat & 0x10) {
155 } else if (spd.cas_lat & 0x08) {
157 } else if (spd.cas_lat & 0x04) {
159 } else if (spd.cas_lat & 0x02) {
161 } else if (spd.cas_lat & 0x01) {
164 puts("DDR:no valid CAS Latency information.\n");
168 tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
169 + (spd.clk_cycle & 0x0f));
170 debug("DDR:Module maximum data rate is: %dMhz\n", tmp);
172 tmp1 = get_bus_freq(0) / 1000000;
173 if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
174 /* 90~230 range, treated as DDR 200 */
175 if (spd.clk_cycle3 == 0xa0)
177 else if(spd.clk_cycle2 == 0xa0)
179 } else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
180 /* 230-280 range, treated as DDR 266 */
181 if (spd.clk_cycle3 == 0x75)
183 else if (spd.clk_cycle2 == 0x75)
185 } else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
186 /* 280~350 range, treated as DDR 333 */
187 if (spd.clk_cycle3 == 0x60)
189 else if (spd.clk_cycle2 == 0x60)
191 } else if (tmp1 < 90 || tmp1 >= 350) {
192 /* DDR rate out-of-range */
193 puts("DDR:platform frequency is not fit for DDR rate\n");
198 * note: caslat must also be programmed into ddr->sdram_mode
201 * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
202 * use conservative value here.
204 trfc = spd.trfc * 1000; /* up to ps */
205 trfc_clk = picos_to_clk(trfc);
206 trfc_low = (trfc_clk - 8) & 0xf;
209 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
210 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
211 ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
212 ((caslat & 0x07) << 16 ) |
215 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
217 ddr->timing_cfg_2 = 0x00000800;
219 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
220 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
223 * Only DDR I is supported
224 * DDR I and II have different mode-register-set definition
227 /* burst length is always 4 */
230 ddr->sdram_mode = 0x52; /* 1.5 */
233 ddr->sdram_mode = 0x22; /* 2.0 */
236 ddr->sdram_mode = 0x62; /* 2.5 */
239 ddr->sdram_mode = 0x32; /* 3.0 */
242 puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
245 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
247 switch(spd.refresh) {
250 tmp = picos_to_clk(15625000);
254 tmp = picos_to_clk(3900000);
258 tmp = picos_to_clk(7800000);
262 tmp = picos_to_clk(31300000);
266 tmp = picos_to_clk(62500000);
270 tmp = picos_to_clk(125000000);
278 * Set BSTOPRE to 0x100 for page mode
279 * If auto-charge is used, set BSTOPRE = 0
281 ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
282 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
285 * Is this an ECC DDR chip?
287 #if defined(CONFIG_DDR_ECC)
288 if (spd.config == 0x02) {
289 /* disable error detection */
290 ddr->err_disable = ~ECC_ERROR_ENABLE;
292 /* set single bit error threshold to maximum value,
293 * reset counter to zero */
294 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
295 (0 << ECC_ERROR_MAN_SBEC_SHIFT);
297 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
298 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
306 * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
307 * clock cycle after address/command
309 /*ddr->sdram_clk_cntl = 0x82000000;*/
310 ddr->sdram_clk_cntl = (DDR_SDRAM_CLK_CNTL_SS_EN|DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05);
313 * Figure out the settings for the sdram_cfg register. Build up
314 * the entire register in 'tmp' before writing since the write into
315 * the register will actually enable the memory controller, and all
316 * settings must be done before enabling.
318 * sdram_cfg[0] = 1 (ddr sdram logic enable)
319 * sdram_cfg[1] = 1 (self-refresh-enable)
320 * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
325 * sdram_cfg[3] = RD_EN - registered DIMM enable
326 * A value of 0x26 indicates micron registered DIMMS (micron.com)
328 if (spd.mod_attr == 0x26) {
332 #if defined(CONFIG_DDR_ECC)
334 * If the user wanted ECC (enabled via sdram_cfg[2])
336 if (spd.config == 0x02) {
337 tmp |= SDRAM_CFG_ECC_EN;
341 #if defined(CONFIG_DDR_2T_TIMING)
343 * Enable 2T timing by setting sdram_cfg[16].
345 tmp |= SDRAM_CFG_2T_EN;
348 ddr->sdram_cfg = tmp;
352 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
354 return memsize;/*in MBytes*/
356 #endif /* CONFIG_SPD_EEPROM */
359 #if defined(CONFIG_DDR_ECC)
361 * Use timebase counter, get_timer() is not availabe
362 * at this point of initialization yet.
364 static __inline__ unsigned long get_tbms (void)
367 unsigned long tbu1, tbu2;
369 unsigned long long tmp;
371 ulong tbclk = get_tbclk();
373 /* get the timebase ticks */
375 asm volatile ("mftbu %0":"=r" (tbu1):);
376 asm volatile ("mftb %0":"=r" (tbl):);
377 asm volatile ("mftbu %0":"=r" (tbu2):);
378 } while (tbu1 != tbu2);
380 /* convert ticks to ms */
381 tmp = (unsigned long long)(tbu1);
383 tmp += (unsigned long long)(tbl);
384 ms = tmp/(tbclk/1000);
390 * Initialize all of memory for ECC, then enable errors.
392 //#define CONFIG_DDR_ECC_INIT_VIA_DMA
393 void ddr_enable_ecc(unsigned int dram_size)
396 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
397 volatile ddr8349_t *ddr = &immap->ddr;
398 unsigned long t_start, t_end;
399 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
403 debug("Initialize a Cachline in DRAM\n");
406 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
407 /* Initialise DMA for direct Transfers */
411 t_start = get_tbms();
413 #if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
414 debug("DDR init: Cache flush method\n");
415 for (p = 0; p < (uint *)(dram_size); p++) {
416 if (((unsigned int)p & 0x1f) == 0) {
417 ppcDcbz((unsigned long) p);
420 /* write pattern to cache and flush */
421 *p = (unsigned int)0xdeadbeef;
423 if (((unsigned int)p & 0x1c) == 0x1c) {
424 ppcDcbf((unsigned long) p);
428 printf("DDR init: DMA method\n");
429 for (p = 0; p < (uint *)(8 * 1024); p++) {
430 /* zero one data cache line */
431 if (((unsigned int)p & 0x1f) == 0) {
432 ppcDcbz((unsigned long)p);
435 /* write pattern to it and flush */
436 *p = (unsigned int)0xdeadbeef;
438 if (((unsigned int)p & 0x1c) == 0x1c) {
439 ppcDcbf((unsigned long)p);
444 dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
446 dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
448 dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
450 dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
452 dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
454 dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
456 dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
458 dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
460 dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
462 dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
464 for (i = 1; i < dram_size / 0x800000; i++) {
465 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
472 debug("\nREADY!!\n");
473 debug("ddr init duration: %ld ms\n", t_end - t_start);
475 /* Clear All ECC Errors */
476 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
477 ddr->err_detect |= ECC_ERROR_DETECT_MME;
478 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
479 ddr->err_detect |= ECC_ERROR_DETECT_MBE;
480 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
481 ddr->err_detect |= ECC_ERROR_DETECT_SBE;
482 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
483 ddr->err_detect |= ECC_ERROR_DETECT_MSE;
485 /* Disable ECC-Interrupts */
486 ddr->err_int_en &= ECC_ERR_INT_DISABLE;
488 /* Enable errors for ECC */
489 ddr->err_disable &= ECC_ERROR_ENABLE;
491 __asm__ __volatile__ ("sync");
492 __asm__ __volatile__ ("isync");
494 #endif /* CONFIG_DDR_ECC */