2 * (C) Copyright 2006 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
8 * (C) Copyright 2003 Motorola Inc.
9 * Xianghua Xiao (X.Xiao@motorola.com)
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/processor.h>
35 #include <spd_sdram.h>
37 #ifdef CONFIG_SPD_EEPROM
39 DECLARE_GLOBAL_DATA_PTR;
41 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
42 extern void dma_init(void);
43 extern uint dma_check(void);
44 extern int dma_xfer(void *dest, uint count, void *src);
48 #define CFG_READ_SPD i2c_read
52 * Convert picoseconds into clock cycles (rounding up if needed).
55 picos_to_clk(int picos)
57 unsigned int ddr_bus_clk;
60 ddr_bus_clk = gd->ddr_clk >> 1;
61 clks = picos / ((1000000000 / ddr_bus_clk) * 1000);
62 if (picos % ((1000000000 / ddr_bus_clk) * 1000) != 0)
68 unsigned int banksize(unsigned char row_dens)
70 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
73 int read_spd(uint addr)
80 static void spd_debug(spd_eeprom_t *spd)
82 printf ("\nDIMM type: %-18.18s\n", spd->mpart);
83 printf ("SPD size: %d\n", spd->info_size);
84 printf ("EEPROM size: %d\n", 1 << spd->chip_size);
85 printf ("Memory type: %d\n", spd->mem_type);
86 printf ("Row addr: %d\n", spd->nrow_addr);
87 printf ("Column addr: %d\n", spd->ncol_addr);
88 printf ("# of rows: %d\n", spd->nrows);
89 printf ("Row density: %d\n", spd->row_dens);
90 printf ("# of banks: %d\n", spd->nbanks);
91 printf ("Data width: %d\n",
92 256 * spd->dataw_msb + spd->dataw_lsb);
93 printf ("Chip width: %d\n", spd->primw);
94 printf ("Refresh rate: %02X\n", spd->refresh);
95 printf ("CAS latencies: %02X\n", spd->cas_lat);
96 printf ("Write latencies: %02X\n", spd->write_lat);
97 printf ("tRP: %d\n", spd->trp);
98 printf ("tRCD: %d\n", spd->trcd);
101 #endif /* SPD_DEBUG */
105 volatile immap_t *immap = (immap_t *)CFG_IMMR;
106 volatile ddr83xx_t *ddr = &immap->ddr;
107 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
109 unsigned int memsize;
110 unsigned int law_size;
111 unsigned char caslat, caslat_ctrl;
112 unsigned char burstlen;
113 unsigned int max_bus_clk;
114 unsigned int max_data_rate, effective_data_rate;
115 unsigned int ddrc_clk;
116 unsigned int refresh_clk;
118 unsigned int ddrc_ecc_enable;
120 /* Read SPD parameters with I2C */
121 CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
125 /* Check the memory type */
126 if (spd.mem_type != SPD_MEMTYPE_DDR) {
127 printf("DDR: Module mem type is %02X\n", spd.mem_type);
131 /* Check the number of physical bank */
133 printf("DDR: The number of physical bank is %02X\n", spd.nrows);
137 /* Check if the number of row of the module is in the range of DDRC */
138 if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
139 printf("DDR: Row number is out of range of DDRC, row=%02X\n",
144 /* Check if the number of col of the module is in the range of DDRC */
145 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
146 printf("DDR: Col number is out of range of DDRC, col=%02X\n",
150 /* Setup DDR chip select register */
151 #ifdef CFG_83XX_DDR_USES_CS0
152 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
153 ddr->cs_config[0] = ( 1 << 31
154 | (spd.nrow_addr - 12) << 8
155 | (spd.ncol_addr - 8) );
157 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
158 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
160 if (spd.nrows == 2) {
161 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
162 | ((banksize(spd.row_dens) >> 23) - 1) );
163 ddr->cs_config[1] = ( 1<<31
164 | (spd.nrow_addr-12) << 8
165 | (spd.ncol_addr-8) );
166 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
167 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
171 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
172 ddr->cs_config[2] = ( 1 << 31
173 | (spd.nrow_addr - 12) << 8
174 | (spd.ncol_addr - 8) );
176 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
177 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
179 if (spd.nrows == 2) {
180 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
181 | ((banksize(spd.row_dens) >> 23) - 1) );
182 ddr->cs_config[3] = ( 1<<31
183 | (spd.nrow_addr-12) << 8
184 | (spd.ncol_addr-8) );
185 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
186 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
190 if (spd.mem_type != 0x07) {
191 puts("No DDR module found!\n");
196 * Figure out memory size in Megabytes.
198 memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
201 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
203 law_size = 19 + __ilog2(memsize);
206 * Set up LAWBAR for all of DDR.
208 ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
209 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
210 debug("DDR:bar=0x%08x\n", ecm->bar);
211 debug("DDR:ar=0x%08x\n", ecm->ar);
214 * Find the largest CAS by locating the highest 1 bit
215 * in the spd.cas_lat field. Translate it to a DDR
216 * controller field value:
219 * Clocks SPD Bit Value
220 * -------+--------+---------
229 caslat = __ilog2(spd.cas_lat);
232 printf("DDR: Invalid SPD CAS Latency, caslat=%02X\n",
236 max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
237 + (spd.clk_cycle & 0x0f));
238 max_data_rate = max_bus_clk * 2;
240 debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
242 ddrc_clk = gd->ddr_clk / 1000000;
244 if (max_data_rate >= 390) { /* it is DDR 400 */
245 if (ddrc_clk <= 410 && ddrc_clk > 350) {
246 /* DDR controller clk at 350~410 */
247 effective_data_rate = 400; /* 5ns */
249 } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
250 /* DDR controller clk at 280~350 */
251 effective_data_rate = 333; /* 6ns */
252 if (spd.clk_cycle2 == 0x60)
256 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
257 /* DDR controller clk at 230~280 */
258 effective_data_rate = 266; /* 7.5ns */
259 if (spd.clk_cycle3 == 0x75)
261 else if (spd.clk_cycle2 == 0x60)
265 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
266 /* DDR controller clk at 90~230 */
267 effective_data_rate = 200; /* 10ns */
268 if (spd.clk_cycle3 == 0x75)
270 else if (spd.clk_cycle2 == 0x60)
275 } else if (max_data_rate >= 323) { /* it is DDR 333 */
276 if (ddrc_clk <= 350 && ddrc_clk > 280) {
277 /* DDR controller clk at 280~350 */
278 effective_data_rate = 333; /* 6ns */
280 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
281 /* DDR controller clk at 230~280 */
282 effective_data_rate = 266; /* 7.5ns */
283 if (spd.clk_cycle2 == 0x75)
287 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
288 /* DDR controller clk at 90~230 */
289 effective_data_rate = 200; /* 10ns */
290 if (spd.clk_cycle3 == 0xa0)
292 else if (spd.clk_cycle2 == 0x75)
297 } else if (max_data_rate >= 256) { /* it is DDR 266 */
298 if (ddrc_clk <= 350 && ddrc_clk > 280) {
299 /* DDR controller clk at 280~350 */
300 printf("DDR: DDR controller freq is more than "
301 "max data rate of the module\n");
303 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
304 /* DDR controller clk at 230~280 */
305 effective_data_rate = 266; /* 7.5ns */
307 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
308 /* DDR controller clk at 90~230 */
309 effective_data_rate = 200; /* 10ns */
310 if (spd.clk_cycle2 == 0xa0)
313 } else if (max_data_rate >= 190) { /* it is DDR 200 */
314 if (ddrc_clk <= 350 && ddrc_clk > 230) {
315 /* DDR controller clk at 230~350 */
316 printf("DDR: DDR controller freq is more than "
317 "max data rate of the module\n");
319 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
320 /* DDR controller clk at 90~230 */
321 effective_data_rate = 200; /* 10ns */
326 debug("DDR:Effective data rate is: %dMhz\n", effective_data_rate);
327 debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
330 * Errata DDR6 work around: input enable 2 cycles earlier.
331 * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
334 ddr->debug_reg = 0x201c0000; /* CL=2 */
335 else if (caslat == 3)
336 ddr->debug_reg = 0x202c0000; /* CL=2.5 */
337 else if (caslat == 4)
338 ddr->debug_reg = 0x202c0000; /* CL=3.0 */
340 __asm__ __volatile__ ("sync");
342 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
345 * note: caslat must also be programmed into ddr->sdram_mode
348 * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
349 * use conservative value here.
351 caslat_ctrl = (caslat + 1) & 0x07; /* see as above */
354 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
355 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
356 ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
357 ((caslat_ctrl & 0x07) << 16 ) |
358 (((picos_to_clk(spd.trfc * 1000) - 8) & 0x0f) << 12 ) |
360 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
362 ddr->timing_cfg_2 = 0x00000800;
364 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
365 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
366 /* Setup init value, but not enable */
367 ddr->sdram_cfg = 0x42000000;
369 /* Check DIMM data bus width */
370 if (spd.dataw_lsb == 0x20) {
371 burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
372 printf("\n DDR DIMM: data bus width is 32 bit");
374 burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
375 printf("\n DDR DIMM: data bus width is 64 bit");
378 /* Is this an ECC DDR chip? */
379 if (spd.config == 0x02)
380 printf(" with ECC\n");
382 printf(" without ECC\n");
384 /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
385 Burst type is sequential
389 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
392 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
395 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
398 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
401 printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
404 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
406 switch (spd.refresh) {
409 refresh_clk = picos_to_clk(15625000);
413 refresh_clk = picos_to_clk(3900000);
417 refresh_clk = picos_to_clk(7800000);
421 refresh_clk = picos_to_clk(31300000);
425 refresh_clk = picos_to_clk(62500000);
429 refresh_clk = picos_to_clk(125000000);
437 * Set BSTOPRE to 0x100 for page mode
438 * If auto-charge is used, set BSTOPRE = 0
440 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
441 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
443 /* SS_EN = 0, source synchronous disable
444 * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd
446 ddr->sdram_clk_cntl = 0x00000000;
447 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
454 * Figure out the settings for the sdram_cfg register. Build up
455 * the value in 'sdram_cfg' before writing since the write into
456 * the register will actually enable the memory controller, and all
457 * settings must be done before enabling.
459 * sdram_cfg[0] = 1 (ddr sdram logic enable)
460 * sdram_cfg[1] = 1 (self-refresh-enable)
461 * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
462 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
463 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
465 sdram_cfg = 0xC2000000;
467 /* sdram_cfg[3] = RD_EN - registered DIMM enable */
468 if (spd.mod_attr & 0x02)
469 sdram_cfg |= 0x10000000;
471 /* The DIMM is 32bit width */
472 if (spd.dataw_lsb == 0x20)
473 sdram_cfg |= 0x000C0000;
477 #if defined(CONFIG_DDR_ECC)
478 /* Enable ECC with sdram_cfg[2] */
479 if (spd.config == 0x02) {
480 sdram_cfg |= 0x20000000;
482 /* disable error detection */
483 ddr->err_disable = ~ECC_ERROR_ENABLE;
484 /* set single bit error threshold to maximum value,
485 * reset counter to zero */
486 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
487 (0 << ECC_ERROR_MAN_SBEC_SHIFT);
490 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
491 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
493 printf(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
495 #if defined(CONFIG_DDR_2T_TIMING)
497 * Enable 2T timing by setting sdram_cfg[16].
499 sdram_cfg |= SDRAM_CFG_2T_EN;
501 /* Enable controller, and GO! */
502 ddr->sdram_cfg = sdram_cfg;
506 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
507 return memsize; /*in MBytes*/
509 #endif /* CONFIG_SPD_EEPROM */
511 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
513 * Use timebase counter, get_timer() is not availabe
514 * at this point of initialization yet.
516 static __inline__ unsigned long get_tbms (void)
519 unsigned long tbu1, tbu2;
521 unsigned long long tmp;
523 ulong tbclk = get_tbclk();
525 /* get the timebase ticks */
527 asm volatile ("mftbu %0":"=r" (tbu1):);
528 asm volatile ("mftb %0":"=r" (tbl):);
529 asm volatile ("mftbu %0":"=r" (tbu2):);
530 } while (tbu1 != tbu2);
532 /* convert ticks to ms */
533 tmp = (unsigned long long)(tbu1);
535 tmp += (unsigned long long)(tbl);
536 ms = tmp/(tbclk/1000);
542 * Initialize all of memory for ECC, then enable errors.
544 /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
545 void ddr_enable_ecc(unsigned int dram_size)
547 volatile immap_t *immap = (immap_t *)CFG_IMMR;
548 volatile ddr83xx_t *ddr= &immap->ddr;
549 unsigned long t_start, t_end;
552 unsigned int pattern[2];
553 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
557 t_start = get_tbms();
558 pattern[0] = 0xdeadbeef;
559 pattern[1] = 0xdeadbeef;
561 #if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
562 debug("ddr init: CPU FP write method\n");
564 for (p = 0; p < (u64*)(size); p++) {
565 ppcDWstore((u32*)p, pattern);
567 __asm__ __volatile__ ("sync");
569 debug("ddr init: DMA method\n");
571 for (p = 0; p < (u64*)(size); p++) {
572 ppcDWstore((u32*)p, pattern);
574 __asm__ __volatile__ ("sync");
576 /* Initialise DMA for direct transfer */
578 /* Start DMA to transfer */
579 dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */
580 dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */
581 dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */
582 dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */
583 dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */
584 dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */
585 dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */
586 dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
587 dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
588 dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
590 for (i = 1; i < dram_size / 0x800000; i++) {
591 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
598 debug("\nREADY!!\n");
599 debug("ddr init duration: %ld ms\n", t_end - t_start);
601 /* Clear All ECC Errors */
602 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
603 ddr->err_detect |= ECC_ERROR_DETECT_MME;
604 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
605 ddr->err_detect |= ECC_ERROR_DETECT_MBE;
606 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
607 ddr->err_detect |= ECC_ERROR_DETECT_SBE;
608 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
609 ddr->err_detect |= ECC_ERROR_DETECT_MSE;
611 /* Disable ECC-Interrupts */
612 ddr->err_int_en &= ECC_ERR_INT_DISABLE;
614 /* Enable errors for ECC */
615 ddr->err_disable &= ECC_ERROR_ENABLE;
617 __asm__ __volatile__ ("sync");
618 __asm__ __volatile__ ("isync");
620 #endif /* CONFIG_DDR_ECC */