2 * (C) Copyright 2006 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Copyright 2004 Freescale Semiconductor.
8 * (C) Copyright 2003 Motorola Inc.
9 * Xianghua Xiao (X.Xiao@motorola.com)
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * 20050101: Eran Liberty (liberty@freescale.com)
32 * Initial file creating (porting from 85XX & 8260)
33 * 20060601: Dave Liu (daveliu@freescale.com)
35 * unify variable names for 83xx
40 #include <asm/processor.h>
44 #include <spd_sdram.h>
46 #ifdef CONFIG_SPD_EEPROM
48 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
49 extern void dma_init(void);
50 extern uint dma_check(void);
51 extern int dma_xfer(void *dest, uint count, void *src);
55 #define CFG_READ_SPD i2c_read
59 * Convert picoseconds into clock cycles (rounding up if needed).
61 extern ulong get_ddr_clk(ulong dummy);
64 picos_to_clk(int picos)
66 unsigned int ddr_bus_clk;
69 ddr_bus_clk = get_ddr_clk(0) >> 1;
70 clks = picos / ((1000000000 / ddr_bus_clk) * 1000);
71 if (picos % ((1000000000 / ddr_bus_clk) * 1000) !=0) {
78 unsigned int banksize(unsigned char row_dens)
80 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
83 int read_spd(uint addr)
90 static void spd_debug(spd_eeprom_t *spd)
92 printf ("\nDIMM type: %-18.18s\n", spd->mpart);
93 printf ("SPD size: %d\n", spd->info_size);
94 printf ("EEPROM size: %d\n", 1 << spd->chip_size);
95 printf ("Memory type: %d\n", spd->mem_type);
96 printf ("Row addr: %d\n", spd->nrow_addr);
97 printf ("Column addr: %d\n", spd->ncol_addr);
98 printf ("# of rows: %d\n", spd->nrows);
99 printf ("Row density: %d\n", spd->row_dens);
100 printf ("# of banks: %d\n", spd->nbanks);
101 printf ("Data width: %d\n",
102 256 * spd->dataw_msb + spd->dataw_lsb);
103 printf ("Chip width: %d\n", spd->primw);
104 printf ("Refresh rate: %02X\n", spd->refresh);
105 printf ("CAS latencies: %02X\n", spd->cas_lat);
106 printf ("Write latencies: %02X\n", spd->write_lat);
107 printf ("tRP: %d\n", spd->trp);
108 printf ("tRCD: %d\n", spd->trcd);
111 #endif /* SPD_DEBUG */
115 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
116 volatile ddr83xx_t *ddr = &immap->ddr;
117 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
120 unsigned int memsize;
121 unsigned int law_size;
122 unsigned char caslat, caslat_ctrl;
123 unsigned char burstlen;
124 unsigned int max_bus_clk;
125 unsigned int max_data_rate, effective_data_rate;
126 unsigned int ddrc_clk;
127 unsigned int refresh_clk;
129 unsigned int ddrc_ecc_enable;
132 /* Read SPD parameters with I2C */
133 CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
137 /* Check the memory type */
138 if (spd.mem_type != SPD_MEMTYPE_DDR) {
139 printf("DDR: Module mem type is %02X\n", spd.mem_type);
143 /* Check the number of physical bank */
145 printf("DDR: The number of physical bank is %02X\n", spd.nrows);
149 /* Check if the number of row of the module is in the range of DDRC */
150 if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
151 printf("DDR: Row number is out of range of DDRC, row=%02X\n",
156 /* Check if the number of col of the module is in the range of DDRC */
157 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
158 printf("DDR: Col number is out of range of DDRC, col=%02X\n",
162 /* Setup DDR chip select register */
163 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
164 ddr->cs_config[2] = ( 1 << 31
165 | (spd.nrow_addr - 12) << 8
166 | (spd.ncol_addr - 8) );
168 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
169 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
171 if (spd.nrows == 2) {
172 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
173 | ((banksize(spd.row_dens) >> 23) - 1) );
174 ddr->cs_config[3] = ( 1<<31
175 | (spd.nrow_addr-12) << 8
176 | (spd.ncol_addr-8) );
177 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
178 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
181 if (spd.mem_type != 0x07) {
182 puts("No DDR module found!\n");
187 * Figure out memory size in Megabytes.
189 memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
192 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
194 law_size = 19 + __ilog2(memsize);
197 * Set up LAWBAR for all of DDR.
199 ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
200 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
201 debug("DDR:bar=0x%08x\n", ecm->bar);
202 debug("DDR:ar=0x%08x\n", ecm->ar);
205 * Find the largest CAS by locating the highest 1 bit
206 * in the spd.cas_lat field. Translate it to a DDR
207 * controller field value:
210 * Clocks SPD Bit Value
211 * -------+--------+---------
220 caslat = __ilog2(spd.cas_lat);
223 printf("DDR: Invalid SPD CAS Latency, caslat=%02X\n", caslat);
226 max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
227 + (spd.clk_cycle & 0x0f));
228 max_data_rate = max_bus_clk * 2;
230 debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
232 ddrc_clk = get_ddr_clk(0) / 1000000;
234 if (max_data_rate >= 390) { /* it is DDR 400 */
235 printf("DDR: platform not support DDR 400\n");
237 } else if (max_data_rate >= 323) { /* it is DDR 333 */
238 if (ddrc_clk <= 350 && ddrc_clk > 280) {
239 /* DDRC clk at 280~350 */
240 effective_data_rate = 333; /* 6ns */
242 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
243 /* DDRC clk at 230~280 */
244 if (spd.clk_cycle2 == 0x75) {
245 effective_data_rate = 266; /* 7.5ns */
248 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
249 /* DDRC clk at 90~230 */
250 if (spd.clk_cycle3 == 0xa0) {
251 effective_data_rate = 200; /* 10ns */
255 } else if (max_data_rate >= 256) { /* it is DDR 266 */
256 if (ddrc_clk <= 350 && ddrc_clk > 280) {
257 /* DDRC clk at 280~350 */
258 printf("DDR: DDR controller freq is more than "
259 "max data rate of the module\n");
261 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
262 /* DDRC clk at 230~280 */
263 effective_data_rate = 266; /* 7.5ns */
265 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
266 /* DDRC clk at 90~230 */
267 if (spd.clk_cycle2 == 0xa0) {
268 effective_data_rate = 200; /* 10ns */
272 } else if (max_data_rate >= 190) { /* it is DDR 200 */
273 if (ddrc_clk <= 350 && ddrc_clk > 230) {
274 /* DDRC clk at 230~350 */
275 printf("DDR: DDR controller freq is more than "
276 "max data rate of the module\n");
278 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
279 /* DDRC clk at 90~230 */
280 effective_data_rate = 200; /* 10ns */
286 * note: caslat must also be programmed into ddr->sdram_mode
289 * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
290 * use conservative value here.
292 caslat_ctrl = (caslat + 1) & 0x07; /* see as above */
295 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
296 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
297 ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
298 ((caslat_ctrl & 0x07) << 16 ) |
299 (((picos_to_clk(spd.trfc * 1000) - 8) & 0x0f) << 12 ) |
301 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
303 ddr->timing_cfg_2 = 0x00000800;
305 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
306 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
307 /* Setup init value, but not enable */
308 ddr->sdram_cfg = 0x42000000;
310 /* Check DIMM data bus width */
311 if (spd.dataw_lsb == 0x20)
313 burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
314 printf("\n DDR DIMM: data bus width is 32 bit");
318 burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
319 printf("\n DDR DIMM: data bus width is 64 bit");
322 /* Is this an ECC DDR chip? */
323 if (spd.config == 0x02) {
324 printf(" with ECC\n");
327 printf(" without ECC\n");
329 /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
330 Burst type is sequential
334 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
337 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
340 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
343 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
346 printf("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 "
350 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
352 switch(spd.refresh) {
355 tmp = picos_to_clk(15625000);
359 tmp = picos_to_clk(3900000);
363 tmp = picos_to_clk(7800000);
367 tmp = picos_to_clk(31300000);
371 tmp = picos_to_clk(62500000);
375 tmp = picos_to_clk(125000000);
383 * Set BSTOPRE to 0x100 for page mode
384 * If auto-charge is used, set BSTOPRE = 0
386 ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
387 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
389 /* SS_EN = 0, source synchronous disable
390 * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd
392 ddr->sdram_clk_cntl = 0x00000000;
393 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
400 * Figure out the settings for the sdram_cfg register. Build up
401 * the entire register in 'tmp' before writing since the write into
402 * the register will actually enable the memory controller, and all
403 * settings must be done before enabling.
405 * sdram_cfg[0] = 1 (ddr sdram logic enable)
406 * sdram_cfg[1] = 1 (self-refresh-enable)
407 * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
408 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
409 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
411 sdram_cfg = 0xC2000000;
413 /* sdram_cfg[3] = RD_EN - registered DIMM enable */
414 if (spd.mod_attr & 0x02) {
415 sdram_cfg |= 0x10000000;
418 /* The DIMM is 32bit width */
419 if (spd.dataw_lsb == 0x20) {
420 sdram_cfg |= 0x000C0000;
424 #if defined(CONFIG_DDR_ECC)
425 /* Enable ECC with sdram_cfg[2] */
426 if (spd.config == 0x02) {
427 sdram_cfg |= 0x20000000;
429 /* disable error detection */
430 ddr->err_disable = ~ECC_ERROR_ENABLE;
431 /* set single bit error threshold to maximum value,
432 * reset counter to zero */
433 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
434 (0 << ECC_ERROR_MAN_SBEC_SHIFT);
437 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
438 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
440 printf(" DDRC ECC mode: %s", ddrc_ecc_enable ? "ON":"OFF");
442 #if defined(CONFIG_DDR_2T_TIMING)
444 * Enable 2T timing by setting sdram_cfg[16].
446 sdram_cfg |= SDRAM_CFG_2T_EN;
448 /* Enable controller, and GO! */
449 ddr->sdram_cfg = sdram_cfg;
453 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
454 return memsize; /*in MBytes*/
456 #endif /* CONFIG_SPD_EEPROM */
459 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
461 * Use timebase counter, get_timer() is not availabe
462 * at this point of initialization yet.
464 static __inline__ unsigned long get_tbms (void)
467 unsigned long tbu1, tbu2;
469 unsigned long long tmp;
471 ulong tbclk = get_tbclk();
473 /* get the timebase ticks */
475 asm volatile ("mftbu %0":"=r" (tbu1):);
476 asm volatile ("mftb %0":"=r" (tbl):);
477 asm volatile ("mftbu %0":"=r" (tbu2):);
478 } while (tbu1 != tbu2);
480 /* convert ticks to ms */
481 tmp = (unsigned long long)(tbu1);
483 tmp += (unsigned long long)(tbl);
484 ms = tmp/(tbclk/1000);
490 * Initialize all of memory for ECC, then enable errors.
492 /* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
493 void ddr_enable_ecc(unsigned int dram_size)
496 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
497 volatile ddr83xx_t *ddr= &immap->ddr;
498 unsigned long t_start, t_end;
499 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
503 debug("Initialize a Cachline in DRAM\n");
506 #if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
507 /* Initialise DMA for direct Transfers */
511 t_start = get_tbms();
513 #if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
514 debug("DDR init: Cache flush method\n");
515 for (p = 0; p < (uint *)(dram_size); p++) {
516 if (((unsigned int)p & 0x1f) == 0) {
517 ppcDcbz((unsigned long) p);
520 /* write pattern to cache and flush */
521 *p = (unsigned int)0xdeadbeef;
523 if (((unsigned int)p & 0x1c) == 0x1c) {
524 ppcDcbf((unsigned long) p);
528 printf("DDR init: DMA method\n");
529 for (p = 0; p < (uint *)(8 * 1024); p++) {
530 /* zero one data cache line */
531 if (((unsigned int)p & 0x1f) == 0) {
532 ppcDcbz((unsigned long)p);
535 /* write pattern to it and flush */
536 *p = (unsigned int)0xdeadbeef;
538 if (((unsigned int)p & 0x1c) == 0x1c) {
539 ppcDcbf((unsigned long)p);
544 dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
546 dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
548 dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
550 dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
552 dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
554 dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
556 dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
558 dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
560 dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
562 dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
564 for (i = 1; i < dram_size / 0x800000; i++) {
565 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
572 debug("\nREADY!!\n");
573 debug("ddr init duration: %ld ms\n", t_end - t_start);
575 /* Clear All ECC Errors */
576 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
577 ddr->err_detect |= ECC_ERROR_DETECT_MME;
578 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
579 ddr->err_detect |= ECC_ERROR_DETECT_MBE;
580 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
581 ddr->err_detect |= ECC_ERROR_DETECT_SBE;
582 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
583 ddr->err_detect |= ECC_ERROR_DETECT_MSE;
585 /* Disable ECC-Interrupts */
586 ddr->err_int_en &= ECC_ERR_INT_DISABLE;
588 /* Enable errors for ECC */
589 ddr->err_disable &= ECC_ERROR_ENABLE;
591 __asm__ __volatile__ ("sync");
592 __asm__ __volatile__ ("isync");
594 #endif /* CONFIG_DDR_ECC */