2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright 2004 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * 20050101: Eran Liberty (liberty@freescale.com)
28 * Initial file creating (porting from 85XX & 8260)
33 #include <asm/processor.h>
35 /* ----------------------------------------------------------------- */
53 mult_t core_csb_ratio;
57 corecnf_t corecnf_tab[] = {
58 { _byp, _byp}, /* 0x00 */
59 { _byp, _byp}, /* 0x01 */
60 { _byp, _byp}, /* 0x02 */
61 { _byp, _byp}, /* 0x03 */
62 { _byp, _byp}, /* 0x04 */
63 { _byp, _byp}, /* 0x05 */
64 { _byp, _byp}, /* 0x06 */
65 { _byp, _byp}, /* 0x07 */
66 { _1x, _x2}, /* 0x08 */
67 { _1x, _x4}, /* 0x09 */
68 { _1x, _x8}, /* 0x0A */
69 { _1x, _x8}, /* 0x0B */
70 {_1_5x, _x2}, /* 0x0C */
71 {_1_5x, _x4}, /* 0x0D */
72 {_1_5x, _x8}, /* 0x0E */
73 {_1_5x, _x8}, /* 0x0F */
74 { _2x, _x2}, /* 0x10 */
75 { _2x, _x4}, /* 0x11 */
76 { _2x, _x8}, /* 0x12 */
77 { _2x, _x8}, /* 0x13 */
78 {_2_5x, _x2}, /* 0x14 */
79 {_2_5x, _x4}, /* 0x15 */
80 {_2_5x, _x8}, /* 0x16 */
81 {_2_5x, _x8}, /* 0x17 */
82 { _3x, _x2}, /* 0x18 */
83 { _3x, _x4}, /* 0x19 */
84 { _3x, _x8}, /* 0x1A */
85 { _3x, _x8}, /* 0x1B */
88 /* ----------------------------------------------------------------- */
95 DECLARE_GLOBAL_DATA_PTR;
96 volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
101 u32 corecnf_tab_index;
117 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
120 #ifndef CFG_HRCW_HIGH
121 # error "CFG_HRCW_HIGH must be defined in include/configs/MCP83XXADS.h"
122 #endif /* CFG_HCWD_HIGH */
124 #if (CFG_HRCW_HIGH & HRCWH_PCI_HOST)
125 # ifndef CONFIG_83XX_CLKIN
126 # error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in include/configs/MCP83XXADS.h"
127 # endif /* CONFIG_83XX_CLKIN */
128 # ifdef CONFIG_83XX_PCICLK
129 # warning "In PCI Host Mode, CONFIG_83XX_PCICLK in include/configs/MCP83XXADS.h is igonred."
130 # endif /* CONFIG_83XX_PCICLK */
132 if (!(im->reset.rcwh & RCWH_PCIHOST)) {
133 /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is disabled */
134 /* FIXME: findout if there is a way to issue some warning */
138 if (im->clk.spmr & SPMR_CKID) {
139 pci_sync_in = CONFIG_83XX_CLKIN / 2; /* PCI Clock is half CONFIG_83XX_CLKIN */
142 pci_sync_in = CONFIG_83XX_CLKIN;
145 # ifdef CONFIG_83XX_CLKIN
146 # warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in include/configs/MCP83XXADS.h is igonred."
147 # endif /* CONFIG_83XX_CLKIN */
148 # ifndef CONFIG_83XX_PCICLK
149 # error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in include/configs/MCP83XXADS.h"
150 # endif /* CONFIG_83XX_PCICLK */
152 if (im->reset.rcwh & RCWH_PCIHOST) {
153 /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is enabled */
156 pci_sync_in = CONFIG_83XX_PCICLK;
157 #endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
159 /* we have up to date pci_sync_in */
161 spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT);
162 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
164 if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) {
165 csb_clk = (pci_sync_in * spmf * (1 + clkin_div)) / 2;
168 csb_clk = pci_sync_in * spmf * (1 + clkin_div);
172 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
180 tsec1_clk = csb_clk / 2;
183 tsec1_clk = csb_clk / 3;
186 /* unkown SCCR_TSEC1CM value */
190 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
198 tsec2_clk = csb_clk / 2;
201 tsec2_clk = csb_clk / 3;
204 /* unkown SCCR_TSEC2CM value */
209 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
217 enc_clk = csb_clk / 2;
220 enc_clk = csb_clk / 3;
223 /* unkown SCCR_ENCCM value */
227 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
232 usbmph_clk = csb_clk;
235 usbmph_clk = csb_clk / 2;
238 usbmph_clk = csb_clk / 3;
241 /* unkown SCCR_USBMPHCM value */
245 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
253 usbdr_clk = csb_clk / 2;
256 usbdr_clk = csb_clk / 3;
259 /* unkown SCCR_USBDRCM value */
265 && usbmph_clk != usbdr_clk ) {
266 /* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */
270 lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
271 lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
276 lclk_clk = lbiu_clk / lcrr;
283 ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
285 corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
286 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
287 if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) {
288 /* corecnf_tab_index is too high, possibly worng value */
291 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
298 core_clk = (3 * csb_clk) / 2;
301 core_clk = 2 * csb_clk;
304 core_clk = ( 5 * csb_clk) / 2;
307 core_clk = 3 * csb_clk;
310 /* unkown core to csb ratio */
314 gd->csb_clk = csb_clk ;
315 gd->tsec1_clk = tsec1_clk ;
316 gd->tsec2_clk = tsec2_clk ;
317 gd->core_clk = core_clk ;
318 gd->usbmph_clk = usbmph_clk;
319 gd->usbdr_clk = usbdr_clk ;
320 gd->i2c_clk = i2c_clk ;
321 gd->enc_clk = enc_clk ;
322 gd->lbiu_clk = lbiu_clk ;
323 gd->lclk_clk = lclk_clk ;
324 gd->ddr_clk = ddr_clk ;
326 gd->cpu_clk = gd->core_clk;
327 gd->bus_clk = gd->lbiu_clk;
331 /********************************************
333 * return system bus freq in Hz
334 *********************************************/
335 ulong get_bus_freq (ulong dummy)
337 DECLARE_GLOBAL_DATA_PTR;
341 int print_clock_conf (void)
343 DECLARE_GLOBAL_DATA_PTR;
345 printf("Clock configuration:\n");
346 printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
347 printf(" Core: %4d MHz\n",gd->core_clk/1000000);
348 printf(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
349 printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000);
350 printf(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
351 printf(" I2C: %4d MHz\n",gd->i2c_clk/1000000);
352 printf(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
353 printf(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
354 printf(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
355 printf(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
358 DECLARE_GLOBAL_DATA_PTR;
360 volatile immap_t *immap = (immap_t *) CFG_IMMR;
362 ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf;
365 sccr = immap->im_clkrst.car_sccr;
366 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
368 scmr = immap->im_clkrst.car_scmr;
369 corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
370 busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
371 cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
372 plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
373 pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
375 cp = &corecnf_tab[corecnf];
377 puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult ");
379 switch (cp->b2c_mult) {
395 (cp->b2c_mult % 2) ? ".5" : "");
399 printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n",
400 cp->vco_div, cp->freq_60x, cp->freq_core);
402 printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, "
403 "plldf %ld, pllmf %ld\n", dfbrg, corecnf, busdf, cpmdf, plldf,
406 printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
407 gd->vco_out, gd->scc_clk, gd->brg_clk);
409 printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n",
410 gd->cpu_clk, gd->cpm_clk, gd->bus_clk);
412 if (sccr & SCCR_PCI_MODE) {
415 pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) *
416 ( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1);
418 printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div);