2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * 20050101: Eran Liberty (liberty@freescale.com)
28 * Initial file creating (porting from 85XX & 8260)
33 #include <asm/processor.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 /* ----------------------------------------------------------------- */
55 mult_t core_csb_ratio;
59 corecnf_t corecnf_tab[] = {
60 {_byp, _byp}, /* 0x00 */
61 {_byp, _byp}, /* 0x01 */
62 {_byp, _byp}, /* 0x02 */
63 {_byp, _byp}, /* 0x03 */
64 {_byp, _byp}, /* 0x04 */
65 {_byp, _byp}, /* 0x05 */
66 {_byp, _byp}, /* 0x06 */
67 {_byp, _byp}, /* 0x07 */
68 {_1x, _x2}, /* 0x08 */
69 {_1x, _x4}, /* 0x09 */
70 {_1x, _x8}, /* 0x0A */
71 {_1x, _x8}, /* 0x0B */
72 {_1_5x, _x2}, /* 0x0C */
73 {_1_5x, _x4}, /* 0x0D */
74 {_1_5x, _x8}, /* 0x0E */
75 {_1_5x, _x8}, /* 0x0F */
76 {_2x, _x2}, /* 0x10 */
77 {_2x, _x4}, /* 0x11 */
78 {_2x, _x8}, /* 0x12 */
79 {_2x, _x8}, /* 0x13 */
80 {_2_5x, _x2}, /* 0x14 */
81 {_2_5x, _x4}, /* 0x15 */
82 {_2_5x, _x8}, /* 0x16 */
83 {_2_5x, _x8}, /* 0x17 */
84 {_3x, _x2}, /* 0x18 */
85 {_3x, _x4}, /* 0x19 */
86 {_3x, _x8}, /* 0x1A */
87 {_3x, _x8}, /* 0x1B */
90 /* ----------------------------------------------------------------- */
97 volatile immap_t *im = (immap_t *) CFG_IMMR;
102 u32 corecnf_tab_index;
107 #if defined(CONFIG_MPC8349)
120 #if defined (CONFIG_MPC8360)
128 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
131 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
133 if (im->reset.rcwh & HRCWH_PCI_HOST) {
134 #if defined(CONFIG_83XX_CLKIN)
135 pci_sync_in = CONFIG_83XX_CLKIN / (1 + clkin_div);
137 pci_sync_in = 0xDEADBEEF;
140 #if defined(CONFIG_83XX_PCICLK)
141 pci_sync_in = CONFIG_83XX_PCICLK;
143 pci_sync_in = 0xDEADBEEF;
147 spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT);
148 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
152 #if defined(CONFIG_MPC8349)
153 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
161 tsec1_clk = csb_clk / 2;
164 tsec1_clk = csb_clk / 3;
167 /* unkown SCCR_TSEC1CM value */
171 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
179 tsec2_clk = csb_clk / 2;
182 tsec2_clk = csb_clk / 3;
185 /* unkown SCCR_TSEC2CM value */
189 i2c1_clk = tsec2_clk;
191 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
196 usbmph_clk = csb_clk;
199 usbmph_clk = csb_clk / 2;
202 usbmph_clk = csb_clk / 3;
205 /* unkown SCCR_USBMPHCM value */
209 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
217 usbdr_clk = csb_clk / 2;
220 usbdr_clk = csb_clk / 3;
223 /* unkown SCCR_USBDRCM value */
227 if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
228 /* if USB MPH clock is not disabled and
229 * USB DR clock is not disabled then
230 * USB MPH & USB DR must have the same rate
235 #if defined (CONFIG_MPC8360)
238 i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
240 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
248 enc_clk = csb_clk / 2;
251 enc_clk = csb_clk / 3;
254 /* unkown SCCR_ENCCM value */
257 #if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
259 (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
261 #error Unknown MPC83xx chip
263 lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
268 lclk_clk = lbiu_clk / lcrr;
274 #if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
276 (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
277 corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
278 #if defined (CONFIG_MPC8360)
279 ddr_sec_clk = csb_clk * (1 +
280 ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
283 #error Unknown MPC83xx chip
286 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
287 if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
288 /* corecnf_tab_index is too high, possibly worng value */
291 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
298 core_clk = (3 * csb_clk) / 2;
301 core_clk = 2 * csb_clk;
304 core_clk = (5 * csb_clk) / 2;
307 core_clk = 3 * csb_clk;
310 /* unkown core to csb ratio */
314 #if defined (CONFIG_MPC8360)
315 qepmf = (im->reset.rcwl & RCWL_CEPMF) >> RCWL_CEPMF_SHIFT;
316 qepdf = (im->reset.rcwl & RCWL_CEPDF) >> RCWL_CEPDF_SHIFT;
317 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
318 brg_clk = qe_clk / 2;
321 gd->csb_clk = csb_clk;
322 #if defined(CONFIG_MPC8349)
323 gd->tsec1_clk = tsec1_clk;
324 gd->tsec2_clk = tsec2_clk;
325 gd->usbmph_clk = usbmph_clk;
326 gd->usbdr_clk = usbdr_clk;
328 gd->core_clk = core_clk;
329 gd->i2c1_clk = i2c1_clk;
330 gd->i2c2_clk = i2c2_clk;
331 gd->enc_clk = enc_clk;
332 gd->lbiu_clk = lbiu_clk;
333 gd->lclk_clk = lclk_clk;
334 gd->ddr_clk = ddr_clk;
335 #if defined (CONFIG_MPC8360)
336 gd->ddr_sec_clk = ddr_sec_clk;
338 gd->brg_clk = brg_clk;
340 gd->cpu_clk = gd->core_clk;
341 gd->bus_clk = gd->csb_clk;
346 ulong get_ddr_clk(ulong dummy)
351 /********************************************
353 * return system bus freq in Hz
354 *********************************************/
355 ulong get_bus_freq(ulong dummy)
360 int print_clock_conf(void)
362 printf("Clock configuration:\n");
363 printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
364 printf(" Core: %4d MHz\n", gd->core_clk / 1000000);
365 #if defined (CONFIG_MPC8360)
366 printf(" QE: %4d MHz\n", gd->qe_clk / 1000000);
368 printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
369 printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000);
370 printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000);
371 #if defined (CONFIG_MPC8360)
372 printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000);
374 printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000);
375 printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000);
376 printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000);
377 #if defined(CONFIG_MPC8349)
378 printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000);
379 printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000);
380 printf(" USB MPH: %4d MHz\n", gd->usbmph_clk / 1000000);
381 printf(" USB DR: %4d MHz\n", gd->usbdr_clk / 1000000);