2 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/cache.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 struct cpu_type cpu_type_list [] = {
40 CPU_TYPE_ENTRY(8533, 8533),
41 CPU_TYPE_ENTRY(8533, 8533_E),
42 CPU_TYPE_ENTRY(8536, 8536),
43 CPU_TYPE_ENTRY(8536, 8536_E),
44 CPU_TYPE_ENTRY(8540, 8540),
45 CPU_TYPE_ENTRY(8541, 8541),
46 CPU_TYPE_ENTRY(8541, 8541_E),
47 CPU_TYPE_ENTRY(8543, 8543),
48 CPU_TYPE_ENTRY(8543, 8543_E),
49 CPU_TYPE_ENTRY(8544, 8544),
50 CPU_TYPE_ENTRY(8544, 8544_E),
51 CPU_TYPE_ENTRY(8545, 8545),
52 CPU_TYPE_ENTRY(8545, 8545_E),
53 CPU_TYPE_ENTRY(8547, 8547_E),
54 CPU_TYPE_ENTRY(8548, 8548),
55 CPU_TYPE_ENTRY(8548, 8548_E),
56 CPU_TYPE_ENTRY(8555, 8555),
57 CPU_TYPE_ENTRY(8555, 8555_E),
58 CPU_TYPE_ENTRY(8560, 8560),
59 CPU_TYPE_ENTRY(8567, 8567),
60 CPU_TYPE_ENTRY(8567, 8567_E),
61 CPU_TYPE_ENTRY(8568, 8568),
62 CPU_TYPE_ENTRY(8568, 8568_E),
63 CPU_TYPE_ENTRY(8572, 8572),
64 CPU_TYPE_ENTRY(8572, 8572_E),
67 struct cpu_type *identify_cpu(u32 ver)
70 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
71 if (cpu_type_list[i].soc_ver == ver)
72 return &cpu_type_list[i];
85 char buf1[32], buf2[32];
86 #ifdef CONFIG_DDR_CLK_FREQ
87 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
88 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
89 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
95 ver = SVR_SOC_VER(svr);
98 major &= 0x7; /* the msb of this nibble is a mfg code */
100 minor = SVR_MIN(svr);
102 #if (CONFIG_NUM_CPUS > 1)
103 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
104 printf("CPU%d: ", pic->whoami);
109 cpu = identify_cpu(ver);
113 if (IS_E_PROCESSOR(svr))
119 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
124 major = PVR_MAJ(pvr);
125 minor = PVR_MIN(pvr);
129 case PVR_FAM(PVR_85xx):
137 if (PVR_MEM(pvr) == 0x03)
140 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
142 get_sys_info(&sysinfo);
144 puts("Clock Configuration:\n");
145 printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor));
146 printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
150 printf(" DDR:%-4s MHz (%s MT/s data rate), ",
151 strmhz(buf1, sysinfo.freqDDRBus/2),
152 strmhz(buf2, sysinfo.freqDDRBus));
155 printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
156 strmhz(buf1, sysinfo.freqDDRBus/2),
157 strmhz(buf2, sysinfo.freqDDRBus));
160 printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
161 strmhz(buf1, sysinfo.freqDDRBus/2),
162 strmhz(buf2, sysinfo.freqDDRBus));
166 if (sysinfo.freqLocalBus > LCRR_CLKDIV)
167 printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
169 printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
170 sysinfo.freqLocalBus);
173 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
176 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
182 /* ------------------------------------------------------------------------- */
184 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
188 unsigned long val, msr;
194 /* e500 v2 core has reset control register */
195 volatile unsigned int * rstcr;
196 rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0);
197 *rstcr = 0x2; /* HRESET_REQ */
202 * Fallthrough if the code above failed
203 * Initiate hard reset in debug control register DBCR0
204 * Make sure MSR[DE] = 1
220 * Get timebase clock frequency
222 unsigned long get_tbclk (void)
224 return (gd->bus_clk + 4UL)/8UL;
228 #if defined(CONFIG_WATCHDOG)
232 int re_enable = disable_interrupts();
233 reset_85xx_watchdog();
234 if (re_enable) enable_interrupts();
238 reset_85xx_watchdog(void)
241 * Clear TSR(WIS) bit by writing 1
244 val = mfspr(SPRN_TSR);
246 mtspr(SPRN_TSR, val);
248 #endif /* CONFIG_WATCHDOG */
250 #if defined(CONFIG_DDR_ECC)
251 void dma_init(void) {
252 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
254 dma->satr0 = 0x02c40000;
255 dma->datr0 = 0x02c40000;
256 dma->sr0 = 0xfffffff; /* clear any errors */
257 asm("sync; isync; msync");
261 uint dma_check(void) {
262 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
263 volatile uint status = dma->sr0;
265 /* While the channel is busy, spin */
266 while((status & 4) == 4) {
270 /* clear MR0[CS] channel start bit */
271 dma->mr0 &= 0x00000001;
272 asm("sync;isync;msync");
275 printf ("DMA Error: status = %x\n", status);
280 int dma_xfer(void *dest, uint count, void *src) {
281 volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
283 dma->dar0 = (uint) dest;
284 dma->sar0 = (uint) src;
286 dma->mr0 = 0xf000004;
287 asm("sync;isync;msync");
288 dma->mr0 = 0xf000005;
289 asm("sync;isync;msync");
295 * Configures a UPM. The function requires the respective MxMR to be set
296 * before calling this function. "size" is the number or entries, not a sizeof.
298 void upmconfig (uint upm, uint * table, uint size)
300 int i, mdr, mad, old_mad = 0;
302 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
303 volatile u32 *brp,*orp;
304 volatile u8* dummy = NULL;
310 upmmask = BR_MS_UPMA;
314 upmmask = BR_MS_UPMB;
318 upmmask = BR_MS_UPMC;
321 printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
325 /* Find the address for the dummy write transaction */
326 for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
327 i++, brp += 2, orp += 2) {
329 /* Look for a valid BR with selected UPM */
330 if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
331 dummy = (volatile u8*)(in_be32(brp) & BR_BA);
337 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
341 for (i = 0; i < size; i++) {
343 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
345 out_be32(&lbc->mdr, table[i]);
347 mdr = in_be32(&lbc->mdr);
349 *(volatile u8 *)dummy = 0;
352 mad = in_be32(mxmr) & MxMR_MAD_MSK;
353 } while (mad <= old_mad && !(!mad && i == (size-1)));
356 out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
361 * Initializes on-chip ethernet controllers.
362 * to override, implement board_eth_init()
364 int cpu_eth_init(bd_t *bis)
366 #if defined(CONFIG_ETHER_ON_FCC)
369 #if defined(CONFIG_UEC_ETH1)
372 #if defined(CONFIG_UEC_ETH2)
375 #if defined(CONFIG_UEC_ETH3)
378 #if defined(CONFIG_UEC_ETH4)
381 #if defined(CONFIG_UEC_ETH5)
384 #if defined(CONFIG_UEC_ETH6)
387 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
388 tsec_standard_init(bis);