2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/cache.h>
33 /* ------------------------------------------------------------------------- */
38 uint lcrr; /* local bus clock ratio register */
39 uint clkdiv; /* clock divider portion of lcrr */
67 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
76 case PVR_VER(PVR_85xx):
83 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
85 get_sys_info(&sysinfo);
87 puts("Clocks Configuration:\n");
88 printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
89 printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
90 printf(" DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
92 #if defined(CFG_LBC_LCRR)
96 volatile immap_t *immap = (immap_t *)CFG_IMMR;
97 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
102 clkdiv = lcrr & 0x0f;
103 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
104 printf("LBC:%4lu MHz\n",
105 sysinfo.freqSystemBus / 1000000 / clkdiv);
107 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
110 if (ver == SVR_8560) {
111 printf("CPM: %lu Mhz\n",
112 sysinfo.freqSystemBus / 1000000);
115 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
121 /* ------------------------------------------------------------------------- */
123 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
126 * Initiate hard reset in debug control register DBCR0
127 * Make sure MSR[DE] = 1
140 * Get timebase clock frequency
142 unsigned long get_tbclk (void)
147 get_sys_info(&sys_info);
148 return ((sys_info.freqSystemBus + 7L) / 8L);
152 #if defined(CONFIG_WATCHDOG)
156 int re_enable = disable_interrupts();
157 reset_85xx_watchdog();
158 if (re_enable) enable_interrupts();
162 reset_85xx_watchdog(void)
165 * Clear TSR(WIS) bit by writing 1
172 #endif /* CONFIG_WATCHDOG */
174 #if defined(CONFIG_DDR_ECC)
175 void dma_init(void) {
176 volatile immap_t *immap = (immap_t *)CFG_IMMR;
177 volatile ccsr_dma_t *dma = &immap->im_dma;
179 dma->satr0 = 0x02c40000;
180 dma->datr0 = 0x02c40000;
181 asm("sync; isync; msync");
185 uint dma_check(void) {
186 volatile immap_t *immap = (immap_t *)CFG_IMMR;
187 volatile ccsr_dma_t *dma = &immap->im_dma;
188 volatile uint status = dma->sr0;
190 /* While the channel is busy, spin */
191 while((status & 4) == 4) {
196 printf ("DMA Error: status = %x\n", status);
201 int dma_xfer(void *dest, uint count, void *src) {
202 volatile immap_t *immap = (immap_t *)CFG_IMMR;
203 volatile ccsr_dma_t *dma = &immap->im_dma;
205 dma->dar0 = (uint) dest;
206 dma->sar0 = (uint) src;
208 dma->mr0 = 0xf000004;
209 asm("sync;isync;msync");
210 dma->mr0 = 0xf000005;
211 asm("sync;isync;msync");