git.sur5r.net Git - u-boot/blob - cpu/mpc85xx/fdt.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <libfdt.h>
  28 #include <fdt_support.h>
  29 #include <asm/processor.h>
  30
  31 DECLARE_GLOBAL_DATA_PTR;
  32
  33 extern void ft_qe_setup(void *blob);
  34
  35 #ifdef CONFIG_MP
  36 #include "mp.h"
  37
  38 void ft_fixup_cpu(void *blob, u64 memory_limit)
  39 {
  40         int off;
  41         ulong spin_tbl_addr = get_spin_addr();
  42         u32 bootpg, id = get_my_id();
  43
  44         /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
  45         if ((u64)gd->ram_size > 0xfffff000)
  46                 bootpg = 0xfffff000;
  47         else
  48                 bootpg = gd->ram_size - 4096;
  49
  50         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  51         while (off != -FDT_ERR_NOTFOUND) {
  52                 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  53
  54                 if (reg) {
  55                         if (*reg == id) {
  56                                 fdt_setprop_string(blob, off, "status", "okay");
  57                         } else {
  58                                 u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
  59                                 val = cpu_to_fdt32(val);
  60                                 fdt_setprop_string(blob, off, "status",
  61                                                                 "disabled");
  62                                 fdt_setprop_string(blob, off, "enable-method",
  63                                                                 "spin-table");
  64                                 fdt_setprop(blob, off, "cpu-release-addr",
  65                                                 &val, sizeof(val));
  66                         }
  67                 } else {
  68                         printf ("cpu NULL\n");
  69                 }
  70                 off = fdt_node_offset_by_prop_value(blob, off,
  71                                 "device_type", "cpu", 4);
  72         }
  73
  74         /* Reserve the boot page so OSes dont use it */
  75         if ((u64)bootpg < memory_limit) {
  76                 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
  77                 if (off < 0)
  78                         printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
  79         }
  80 }
  81 #endif
  82
  83 #define ft_fixup_l3cache(x, y)
  84
  85 #if defined(CONFIG_L2_CACHE)
  86 /* return size in kilobytes */
  87 static inline u32 l2cache_size(void)
  88 {
  89         volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
  90         volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
  91         u32 ver = SVR_SOC_VER(get_svr());
  92
  93         switch (l2siz_field) {
  94         case 0x0:
  95                 break;
  96         case 0x1:
  97                 if (ver == SVR_8540 || ver == SVR_8560   ||
  98                     ver == SVR_8541 || ver == SVR_8541_E ||
  99                     ver == SVR_8555 || ver == SVR_8555_E)
 100                         return 128;
 101                 else
 102                         return 256;
 103                 break;
 104         case 0x2:
 105                 if (ver == SVR_8540 || ver == SVR_8560   ||
 106                     ver == SVR_8541 || ver == SVR_8541_E ||
 107                     ver == SVR_8555 || ver == SVR_8555_E)
 108                         return 256;
 109                 else
 110                         return 512;
 111                 break;
 112         case 0x3:
 113                 return 1024;
 114                 break;
 115         }
 116
 117         return 0;
 118 }
 119
 120 static inline void ft_fixup_l2cache(void *blob)
 121 {
 122         int len, off;
 123         u32 *ph;
 124         struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
 125         char compat_buf[38];
 126
 127         const u32 line_size = 32;
 128         const u32 num_ways = 8;
 129         const u32 size = l2cache_size() * 1024;
 130         const u32 num_sets = size / (line_size * num_ways);
 131
 132         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 133         if (off < 0) {
 134                 debug("no cpu node fount\n");
 135                 return;
 136         }
 137
 138         ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
 139
 140         if (ph == NULL) {
 141                 debug("no next-level-cache property\n");
 142                 return ;
 143         }
 144
 145         off = fdt_node_offset_by_phandle(blob, *ph);
 146         if (off < 0) {
 147                 printf("%s: %s\n", __func__, fdt_strerror(off));
 148                 return ;
 149         }
 150
 151         if (cpu) {
 152                 len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller",
 153                                 cpu->name);
 154                 sprintf(&compat_buf[len + 1], "cache");
 155         }
 156         fdt_setprop(blob, off, "cache-unified", NULL, 0);
 157         fdt_setprop_cell(blob, off, "cache-block-size", line_size);
 158         fdt_setprop_cell(blob, off, "cache-size", size);
 159         fdt_setprop_cell(blob, off, "cache-sets", num_sets);
 160         fdt_setprop_cell(blob, off, "cache-level", 2);
 161         fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
 162
 163         /* we dont bother w/L3 since no platform of this type has one */
 164 }
 165 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
 166 static inline void ft_fixup_l2cache(void *blob)
 167 {
 168         int off, l2_off, l3_off = -1;
 169         u32 *ph;
 170         u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 171         u32 size, line_size, num_ways, num_sets;
 172
 173         size = (l2cfg0 & 0x3fff) * 64 * 1024;
 174         num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
 175         line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
 176         num_sets = size / (line_size * num_ways);
 177
 178         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 179
 180         while (off != -FDT_ERR_NOTFOUND) {
 181                 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
 182
 183                 if (ph == NULL) {
 184                         debug("no next-level-cache property\n");
 185                         goto next;
 186                 }
 187
 188                 l2_off = fdt_node_offset_by_phandle(blob, *ph);
 189                 if (l2_off < 0) {
 190                         printf("%s: %s\n", __func__, fdt_strerror(off));
 191                         goto next;
 192                 }
 193
 194                 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
 195                 fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
 196                 fdt_setprop_cell(blob, l2_off, "cache-size", size);
 197                 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
 198                 fdt_setprop_cell(blob, l2_off, "cache-level", 2);
 199                 fdt_setprop(blob, l2_off, "compatible", "cache", 6);
 200
 201                 if (l3_off < 0) {
 202                         ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
 203
 204                         if (ph == NULL) {
 205                                 debug("no next-level-cache property\n");
 206                                 goto next;
 207                         }
 208                         l3_off = *ph;
 209                 }
 210 next:
 211                 off = fdt_node_offset_by_prop_value(blob, off,
 212                                 "device_type", "cpu", 4);
 213         }
 214         if (l3_off > 0) {
 215                 l3_off = fdt_node_offset_by_phandle(blob, l3_off);
 216                 if (l3_off < 0) {
 217                         printf("%s: %s\n", __func__, fdt_strerror(off));
 218                         return ;
 219                 }
 220                 ft_fixup_l3cache(blob, l3_off);
 221         }
 222 }
 223 #else
 224 #define ft_fixup_l2cache(x)
 225 #endif
 226
 227 static inline void ft_fixup_cache(void *blob)
 228 {
 229         int off;
 230
 231         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 232
 233         while (off != -FDT_ERR_NOTFOUND) {
 234                 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
 235                 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
 236                 u32 isize, iline_size, inum_sets, inum_ways;
 237                 u32 dsize, dline_size, dnum_sets, dnum_ways;
 238
 239                 /* d-side config */
 240                 dsize = (l1cfg0 & 0x7ff) * 1024;
 241                 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
 242                 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
 243                 dnum_sets = dsize / (dline_size * dnum_ways);
 244
 245                 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
 246                 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
 247                 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
 248
 249                 /* i-side config */
 250                 isize = (l1cfg1 & 0x7ff) * 1024;
 251                 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
 252                 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
 253                 inum_sets = isize / (iline_size * inum_ways);
 254
 255                 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
 256                 fdt_setprop_cell(blob, off, "i-cache-size", isize);
 257                 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
 258
 259                 off = fdt_node_offset_by_prop_value(blob, off,
 260                                 "device_type", "cpu", 4);
 261         }
 262
 263         ft_fixup_l2cache(blob);
 264 }
 265
 266
 267 void fdt_add_enet_stashing(void *fdt)
 268 {
 269         do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
 270
 271         do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
 272
 273         do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
 274 }
 275
 276 void ft_cpu_setup(void *blob, bd_t *bd)
 277 {
 278         int off;
 279         int val;
 280         sys_info_t sysinfo;
 281
 282         /* delete crypto node if not on an E-processor */
 283         if (!IS_E_PROCESSOR(get_svr()))
 284                 fdt_fixup_crypto_node(blob, 0);
 285
 286 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
 287     defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
 288         fdt_fixup_ethernet(blob);
 289
 290         fdt_add_enet_stashing(blob);
 291 #endif
 292
 293         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 294                 "timebase-frequency", bd->bi_busfreq / 8, 1);
 295         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 296                 "bus-frequency", bd->bi_busfreq, 1);
 297         get_sys_info(&sysinfo);
 298         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 299         while (off != -FDT_ERR_NOTFOUND) {
 300                 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 301                 val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]);
 302                 fdt_setprop(blob, off, "clock-frequency", &val, 4);
 303                 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
 304                                                         "cpu", 4);
 305         }
 306         do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
 307                 "bus-frequency", bd->bi_busfreq, 1);
 308
 309         do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
 310                 "bus-frequency", gd->lbc_clk, 1);
 311         do_fixup_by_compat_u32(blob, "fsl,elbc",
 312                 "bus-frequency", gd->lbc_clk, 1);
 313 #ifdef CONFIG_QE
 314         ft_qe_setup(blob);
 315 #endif
 316
 317 #ifdef CONFIG_SYS_NS16550
 318         do_fixup_by_compat_u32(blob, "ns16550",
 319                 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 320 #endif
 321
 322 #ifdef CONFIG_CPM2
 323         do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
 324                 "current-speed", bd->bi_baudrate, 1);
 325
 326         do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
 327                 "clock-frequency", bd->bi_brgfreq, 1);
 328 #endif
 329
 330         fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 331
 332 #ifdef CONFIG_MP
 333         ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
 334 #endif
 335
 336         ft_fixup_cache(blob);
 337 }