2 * Copyright 2004 Freescale Semiconductor.
3 * Copyright (C) 2003 Motorola Inc.
4 * Xianghua Xiao (x.xiao@motorola.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * PCI Configuration space access support for MPC85xx PCI Bridge
29 #include <asm/cpm_85xx.h>
33 #if defined(CONFIG_PCI)
35 static struct pci_controller *pci_hose;
38 pci_mpc85xx_init(struct pci_controller *board_hose)
43 volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
44 volatile ccsr_pcix_t *pcix = &immap->im_pcix;
45 volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2;
46 volatile ccsr_gur_t *gur = &immap->im_gur;
47 struct pci_controller * hose;
49 pci_hose = board_hose;
53 hose->first_busno = 0;
54 hose->last_busno = 0xff;
56 pci_setup_indirect(hose,
63 dev = PCI_BDF(hose->first_busno, 0, 0);
64 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
65 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
66 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
69 * Clear non-reserved bits in status register.
71 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
73 if (!(gur->pordevsr & PORDEVSR_PCI)) {
75 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
76 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
77 pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
80 pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
81 pcix->potear1 = 0x00000000;
82 pcix->powbar1 = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff;
83 pcix->powbear1 = 0x00000000;
84 pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
85 POWAR_MEM_WRITE | POWAR_MEM_512M);
87 pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
88 pcix->potear2 = 0x00000000;
89 pcix->powbar2 = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff;
90 pcix->powbear2 = 0x00000000;
91 pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
92 POWAR_IO_WRITE | POWAR_IO_1M);
94 pcix->pitar1 = 0x00000000;
95 pcix->piwbar1 = 0x00000000;
96 pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
97 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
104 pci_set_region(hose->regions + 0,
110 pci_set_region(hose->regions + 1,
116 hose->region_count = 2;
118 pci_register_hose(hose);
120 #if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
122 * This is a SW workaround for an apparent HW problem
123 * in the PCI controller on the MPC85555/41 CDS boards.
124 * The first config cycle must be to a valid, known
125 * device on the PCI bus in order to trick the PCI
126 * controller state machine into a known valid state.
127 * Without this, the first config cycle has the chance
128 * of hanging the controller permanently, just leaving
129 * it in a semi-working state, or leaving it working.
131 * Pick on the Tundra, Device 17, to get it right.
136 pci_hose_read_config_byte(hose,
143 hose->last_busno = pci_hose_scan(hose);
145 #ifdef CONFIG_MPC85XX_PCI2
148 hose->first_busno = pci_hose[0].last_busno + 1;
149 hose->last_busno = 0xff;
151 pci_setup_indirect(hose,
155 dev = PCI_BDF(hose->first_busno, 0, 0);
156 pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
157 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
158 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
161 * Clear non-reserved bits in status register.
163 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
165 pcix2->potar1 = (CFG_PCI2_MEM_BASE >> 12) & 0x000fffff;
166 pcix2->potear1 = 0x00000000;
167 pcix2->powbar1 = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff;
168 pcix2->powbear1 = 0x00000000;
169 pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
170 POWAR_MEM_WRITE | POWAR_MEM_512M);
172 pcix2->potar2 = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff;
173 pcix2->potear2 = 0x00000000;
174 pcix2->powbar2 = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff;
175 pcix2->powbear2 = 0x00000000;
176 pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
177 POWAR_IO_WRITE | POWAR_IO_1M);
179 pcix2->pitar1 = 0x00000000;
180 pcix2->piwbar1 = 0x00000000;
181 pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
182 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
189 pci_set_region(hose->regions + 0,
195 pci_set_region(hose->regions + 1,
201 hose->region_count = 2;
206 pci_register_hose(hose);
208 hose->last_busno = pci_hose_scan(hose);
212 #ifdef CONFIG_OF_FLAT_TREE
214 ft_pci_setup(void *blob, bd_t *bd)
219 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
221 p[0] = pci_hose[0].first_busno;
222 p[1] = pci_hose[0].last_busno;
225 #ifdef CONFIG_MPC85XX_PCI2
226 p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
228 p[0] = pci_hose[1].first_busno;
229 p[1] = pci_hose[1].last_busno;
233 #endif /* CONFIG_OF_FLAT_TREE */
234 #endif /* CONFIG_PCI */