git.sur5r.net Git - u-boot/blob - cpu/mpc85xx/pci.c

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * Copyright (C) 2003 Motorola Inc.
   4  * Xianghua Xiao (x.xiao@motorola.com)
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * PCI Configuration space access support for MPC85xx PCI Bridge
  27  */
  28 #include <common.h>
  29 #include <asm/cpm_85xx.h>
  30 #include <pci.h>
  31
  32 #if defined(CONFIG_PCI)
  33
  34 static struct pci_controller *pci_hose;
  35
  36 void
  37 pci_mpc85xx_init(struct pci_controller *board_hose)
  38 {
  39         u16 reg16;
  40         u32 dev;
  41
  42         volatile immap_t    *immap = (immap_t *)CFG_CCSRBAR;
  43         volatile ccsr_pcix_t *pcix = &immap->im_pcix;
  44 #ifdef CONFIG_MPC85XX_PCI2
  45         volatile ccsr_pcix_t *pcix2 = &immap->im_pcix2;
  46 #endif
  47         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  48         struct pci_controller * hose;
  49
  50         pci_hose = board_hose;
  51
  52         hose = &pci_hose[0];
  53
  54         hose->first_busno = 0;
  55         hose->last_busno = 0xff;
  56
  57         pci_setup_indirect(hose,
  58                            (CFG_IMMR+0x8000),
  59                            (CFG_IMMR+0x8004));
  60
  61         /*
  62          * Hose scan.
  63          */
  64         dev = PCI_BDF(hose->first_busno, 0, 0);
  65         pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
  66         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  67         pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
  68
  69         /*
  70          * Clear non-reserved bits in status register.
  71          */
  72         pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
  73
  74         if (!(gur->pordevsr & PORDEVSR_PCI)) {
  75                 /* PCI-X init */
  76                 if (CONFIG_SYS_CLK_FREQ < 66000000)
  77                         printf("PCI-X will only work at 66 MHz\n");
  78
  79                 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
  80                         | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
  81                 pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
  82         }
  83
  84         pcix->potar1   = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
  85         pcix->potear1  = 0x00000000;
  86         pcix->powbar1  = (CFG_PCI1_MEM_PHYS >> 12) & 0x000fffff;
  87         pcix->powbear1 = 0x00000000;
  88         pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
  89                         POWAR_MEM_WRITE | (__ilog2(CFG_PCI1_MEM_SIZE) - 1));
  90
  91         pcix->potar2  = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
  92         pcix->potear2  = 0x00000000;
  93         pcix->powbar2  = (CFG_PCI1_IO_PHYS >> 12) & 0x000fffff;
  94         pcix->powbear2 = 0x00000000;
  95         pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
  96                         POWAR_IO_WRITE | (__ilog2(CFG_PCI1_IO_SIZE) - 1));
  97
  98         pcix->pitar1 = 0x00000000;
  99         pcix->piwbar1 = 0x00000000;
 100         pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
 101                         PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
 102
 103         pcix->powar3 = 0;
 104         pcix->powar4 = 0;
 105         pcix->piwar2 = 0;
 106         pcix->piwar3 = 0;
 107
 108         pci_set_region(hose->regions + 0,
 109                        CFG_PCI1_MEM_BASE,
 110                        CFG_PCI1_MEM_PHYS,
 111                        CFG_PCI1_MEM_SIZE,
 112                        PCI_REGION_MEM);
 113
 114         pci_set_region(hose->regions + 1,
 115                        CFG_PCI1_IO_BASE,
 116                        CFG_PCI1_IO_PHYS,
 117                        CFG_PCI1_IO_SIZE,
 118                        PCI_REGION_IO);
 119
 120         hose->region_count = 2;
 121
 122         pci_register_hose(hose);
 123
 124 #if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
 125         /*
 126          * This is a SW workaround for an apparent HW problem
 127          * in the PCI controller on the MPC85555/41 CDS boards.
 128          * The first config cycle must be to a valid, known
 129          * device on the PCI bus in order to trick the PCI
 130          * controller state machine into a known valid state.
 131          * Without this, the first config cycle has the chance
 132          * of hanging the controller permanently, just leaving
 133          * it in a semi-working state, or leaving it working.
 134          *
 135          * Pick on the Tundra, Device 17, to get it right.
 136          */
 137         {
 138                 u8 header_type;
 139
 140                 pci_hose_read_config_byte(hose,
 141                                           PCI_BDF(0,BRIDGE_ID,0),
 142                                           PCI_HEADER_TYPE,
 143                                           &header_type);
 144         }
 145 #endif
 146
 147         hose->last_busno = pci_hose_scan(hose);
 148
 149 #ifdef CONFIG_MPC85XX_PCI2
 150         hose = &pci_hose[1];
 151
 152         hose->first_busno = pci_hose[0].last_busno + 1;
 153         hose->last_busno = 0xff;
 154
 155         pci_setup_indirect(hose,
 156                            (CFG_IMMR+0x9000),
 157                            (CFG_IMMR+0x9004));
 158
 159         dev = PCI_BDF(hose->first_busno, 0, 0);
 160         pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
 161         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 162         pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
 163
 164         /*
 165          * Clear non-reserved bits in status register.
 166          */
 167         pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
 168
 169         pcix2->potar1   = (CFG_PCI2_MEM_BASE >> 12) & 0x000fffff;
 170         pcix2->potear1  = 0x00000000;
 171         pcix2->powbar1  = (CFG_PCI2_MEM_PHYS >> 12) & 0x000fffff;
 172         pcix2->powbear1 = 0x00000000;
 173         pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
 174                         POWAR_MEM_WRITE | (__ilog2(CFG_PCI2_MEM_SIZE) - 1));
 175
 176         pcix2->potar2  = (CFG_PCI2_IO_BASE >> 12) & 0x000fffff;
 177         pcix2->potear2  = 0x00000000;
 178         pcix2->powbar2  = (CFG_PCI2_IO_PHYS >> 12) & 0x000fffff;
 179         pcix2->powbear2 = 0x00000000;
 180         pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
 181                         POWAR_IO_WRITE | (__ilog2(CFG_PCI2_IO_SIZE) - 1));
 182
 183         pcix2->pitar1 = 0x00000000;
 184         pcix2->piwbar1 = 0x00000000;
 185         pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
 186                         PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
 187
 188         pcix2->powar3 = 0;
 189         pcix2->powar4 = 0;
 190         pcix2->piwar2 = 0;
 191         pcix2->piwar3 = 0;
 192
 193         pci_set_region(hose->regions + 0,
 194                        CFG_PCI2_MEM_BASE,
 195                        CFG_PCI2_MEM_PHYS,
 196                        CFG_PCI2_MEM_SIZE,
 197                        PCI_REGION_MEM);
 198
 199         pci_set_region(hose->regions + 1,
 200                        CFG_PCI2_IO_BASE,
 201                        CFG_PCI2_IO_PHYS,
 202                        CFG_PCI2_IO_SIZE,
 203                        PCI_REGION_IO);
 204
 205         hose->region_count = 2;
 206
 207         /*
 208          * Hose scan.
 209          */
 210         pci_register_hose(hose);
 211
 212         hose->last_busno = pci_hose_scan(hose);
 213 #endif
 214 }
 215 #endif /* CONFIG_PCI */