2 * Copyright 2004, 2007-2009 Freescale Semiconductor Inc.
3 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <ppc_asm.tmpl>
30 #include <asm/processor.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 /* --------------------------------------------------------------- */
37 void get_sys_info (sys_info_t * sysInfo)
39 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
40 uint plat_ratio,e500_ratio,half_freqSystemBus;
47 plat_ratio = (gur->porpllsr) & 0x0000003e;
49 sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
51 /* Divide before multiply to avoid integer
52 * overflow for processor speeds above 2GHz */
53 half_freqSystemBus = sysInfo->freqSystemBus/2;
54 for (i = 0; i < CONFIG_NUM_CPUS; i++) {
55 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
56 sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
59 /* Note: freqDDRBus is the MCLK frequency, not the data rate. */
60 sysInfo->freqDDRBus = sysInfo->freqSystemBus;
62 #ifdef CONFIG_DDR_CLK_FREQ
64 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
65 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
67 sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
72 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
73 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
74 sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
77 #if defined(CONFIG_SYS_LBC_LCRR)
78 /* We will program LCRR to this value later */
79 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
82 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
83 lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
86 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
87 #if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
88 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
90 * Yes, the entire PQ38 family use the same
91 * bit-representation for twice the clock divider values.
95 sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
97 /* In case anyone cares what the unknown value is */
98 sysInfo->freqLocalBus = lcrr_div;
103 int get_clocks (void)
106 #ifdef CONFIG_MPC8544
107 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
109 #if defined(CONFIG_CPM2)
110 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
113 /* set VCO = 4 * BRG */
114 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
115 sccr = cpm->im_cpm_intctl.sccr;
116 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
118 get_sys_info (&sys_info);
119 gd->cpu_clk = sys_info.freqProcessor[0];
120 gd->bus_clk = sys_info.freqSystemBus;
121 gd->mem_clk = sys_info.freqDDRBus;
122 gd->lbc_clk = sys_info.freqLocalBus;
125 gd->qe_clk = sys_info.freqQE;
126 gd->brg_clk = gd->qe_clk / 2;
129 * The base clock for I2C depends on the actual SOC. Unfortunately,
130 * there is no pattern that can be used to determine the frequency, so
131 * the only choice is to look up the actual SOC number and use the value
132 * for that SOC. This information is taken from application note
135 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
136 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
137 gd->i2c1_clk = sys_info.freqSystemBus;
138 #elif defined(CONFIG_MPC8544)
140 * On the 8544, the I2C clock is the same as the SEC clock. This can be
141 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
142 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
143 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
144 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
146 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
147 gd->i2c1_clk = sys_info.freqSystemBus / 3;
149 gd->i2c1_clk = sys_info.freqSystemBus / 2;
151 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
152 gd->i2c1_clk = sys_info.freqSystemBus / 2;
154 gd->i2c2_clk = gd->i2c1_clk;
156 #if defined(CONFIG_MPC8536)
157 gd->sdhc_clk = gd->bus_clk / 2;
160 #if defined(CONFIG_CPM2)
161 gd->vco_out = 2*sys_info.freqSystemBus;
162 gd->cpm_clk = gd->vco_out / 2;
163 gd->scc_clk = gd->vco_out / 4;
164 gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
167 if(gd->cpu_clk != 0) return (0);
172 /********************************************
174 * return system bus freq in Hz
175 *********************************************/
176 ulong get_bus_freq (ulong dummy)
181 /********************************************
183 * return ddr bus freq in Hz
184 *********************************************/
185 ulong get_ddr_freq (ulong dummy)