2 * Copyright 2004 Freescale Semiconductor.
3 * Copyright (C) 2003 Motorola,Inc.
4 * Xianghua Xiao<X.Xiao@motorola.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
27 * The processor starts at 0xfffffffc and the code is first executed in the
28 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
36 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
44 #ifndef CONFIG_IDENT_STRING
45 #define CONFIG_IDENT_STRING ""
49 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
52 * Set up GOT: Global Offset Table
54 * Use r14 to access the GOT
57 GOT_ENTRY(_GOT2_TABLE_)
58 GOT_ENTRY(_FIXUP_TABLE_)
61 GOT_ENTRY(_start_of_vectors)
62 GOT_ENTRY(_end_of_vectors)
63 GOT_ENTRY(transfer_to_handler)
67 GOT_ENTRY(__bss_start)
71 * e500 Startup -- after reset only the last 4KB of the effective
72 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
73 * section is located at THIS LAST page and basically does three
74 * things: clear some registers, set up exception tables and
75 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
76 * continue the boot procedure.
78 * Once the boot rom is mapped by TLB entries we can proceed
79 * with normal startup.
88 lis r1, PVR_85xx_REV1@h
89 ori r1, r1, PVR_85xx_REV1@l
93 /* Semi-bogus errata fixup for Rev 1 */
98 * Before invalidating MMU L1/L2, read TLB1 Entry 0 and then
99 * write it back immediately to fixup a Rev 1 bug (Errata CPU4)
100 * for this initial TLB1 entry 0, otherwise the TLB1 entry 0
101 * will be invalidated (incorrectly).
111 * Clear and set up some registers.
112 * Note: Some registers need strict synchronization by
113 * sync/mbar/msync/isync when being "mtspr".
114 * BookE: isync before PID,tlbivax,tlbwe
115 * BookE: isync after MSR,PID; msync_isync after tlbivax & tlbwe
116 * E500: msync,isync before L1CSR0
117 * E500: isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1,
118 * L1CSR0, L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2],
122 /* invalidate d-cache */
130 /* disable d-cache */
135 /* invalidate i-cache */
141 /* disable i-cache */
146 /* clear registers */
172 mtspr DBSR,r1 /* Clear all valid bits */
184 mtspr BUCSR,r0 /* disable branch prediction */
197 /* Setup interrupt vectors */
202 mtspr IVOR0,r1 /* 0: Critical input */
204 mtspr IVOR1,r1 /* 1: Machine check */
206 mtspr IVOR2,r1 /* 2: Data storage */
208 mtspr IVOR3,r1 /* 3: Instruction storage */
210 mtspr IVOR4,r1 /* 4: External interrupt */
212 mtspr IVOR5,r1 /* 5: Alignment */
214 mtspr IVOR6,r1 /* 6: Program check */
216 mtspr IVOR7,r1 /* 7: floating point unavailable */
218 mtspr IVOR8,r1 /* 8: System call */
219 /* 9: Auxiliary processor unavailable(unsupported) */
221 mtspr IVOR10,r1 /* 10: Decrementer */
223 mtspr IVOR13,r1 /* 13: Data TLB error */
225 mtspr IVOR14,r1 /* 14: Instruction TLB error */
227 mtspr IVOR15,r1 /* 15: Debug */
230 * Invalidate MMU L1/L2
232 * Note: There is a fixup earlier for Errata CPU4 on
233 * Rev 1 parts that must precede this MMU invalidation.
239 /* After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
240 * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
241 * region before we can access any CCSR registers such as L2
242 * registers, Local Access Registers,etc. We will also re-allocate
243 * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup.
245 * Please refer to board-specif directory for TLB1 entry configuration.
246 * (e.g. board/<yourboard>/init.S)
251 li r1,0x000f /* max 16 TLB1 entries */
253 lwzu r4,0(r5) /* how many TLB1 entries we actually use */
273 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
274 /* Special sequence needed to update CCSRBAR itself */
275 lis r4, CFG_CCSRBAR_DEFAULT@h
276 ori r4, r4, CFG_CCSRBAR_DEFAULT@l
278 lis r5, CFG_CCSRBAR@h
279 ori r5, r5, CFG_CCSRBAR@l
289 lis r3, CFG_CCSRBAR@h
290 lwz r5, CFG_CCSRBAR@l(r3)
294 /* invalidate all TLB0 entries */
299 * To avoid REV1 Errata CPU6 issues, make sure
300 * the instruction following tlbivax is not a store.
304 /* set up local access windows, defined at board/<boardname>/init.S */
306 ori r7,r7,CFG_CCSRBAR@l
310 #if defined(CONFIG_RAM_AS_FLASH)
313 li r1,0x0007 /*we have 8 LAWs, but reseve one for boot-over-rio-or-pci */
316 lwzu r5,0(r6) /* how many windows we actually use */
318 #if defined(CONFIG_RAM_AS_FLASH)
322 li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */
337 /* Jump out the last 4K page and continue to 'normal' start */
342 mtspr SRR1,r0 /* Keep things disabled for now */
348 * r3 - 1st arg to board_init(): IMMP pointer
349 * r4 - 2nd arg to board_init(): boot flag
352 .long 0x27051956 /* U-BOOT Magic Number */
353 .globl version_string
355 .ascii U_BOOT_VERSION
356 .ascii " (", __DATE__, " - ", __TIME__, ")"
357 .ascii CONFIG_IDENT_STRING, "\0"
359 . = EXC_OFF_SYS_RESET
362 /* Clear and set up some registers. */
365 mtspr DEC,r0 /* prevent dec exceptions */
366 mttbl r0 /* prevent fit & wdt exceptions */
368 mtspr TSR,r1 /* clear all timer exception status */
369 mtspr TCR,r0 /* disable all */
370 mtspr ESR,r0 /* clear exception syndrome register */
371 mtspr MCSR,r0 /* machine check syndrome register */
372 mtxer r0 /* clear integer exception register */
373 lis r1,0x0002 /* set CE bit (Critical Exceptions) */
374 ori r1,r1,0x1200 /* set ME/DE bit */
375 mtmsr r1 /* change MSR */
378 /* Enable Time Base and Select Time Base Clock */
379 li r0,0x4000 /* time base is processor clock */
383 #if defined(CONFIG_ADDR_STREAMING)
391 /* Enable Branch Prediction */
392 #if defined(CONFIG_BTB)
393 li r0,0x201 /* BBFI = 1, BPEN = 1 */
398 #if defined(CFG_INIT_DBCR)
401 mtspr dbsr,r1 /* Clear all status bits */
402 lis r0,CFG_INIT_DBCR@h /* DBCR0[IDM] must be set */
403 ori r0,r0,CFG_INIT_DBCR@l
408 /* L1 DCache is used for initial RAM */
414 mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */
417 /* Allocate Initial RAM in data cache.
419 lis r3, CFG_INIT_RAM_ADDR@h
420 ori r3, r3, CFG_INIT_RAM_ADDR@l
421 li r2, 512 /* 512*32=16K */
431 /* Calculate absolute address in FLASH and jump there */
432 /*--------------------------------------------------------------*/
433 lis r3, CFG_MONITOR_BASE@h
434 ori r3, r3, CFG_MONITOR_BASE@l
435 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
440 #endif /* CFG_RAMBOOT */
442 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
443 lis r1,CFG_INIT_RAM_ADDR@h
444 ori r1,r1,CFG_INIT_SP_OFFSET@l
448 stwu r0,-4(r1) /* Terminate call chain */
450 stwu r1,-8(r1) /* Save back chain and move SP */
451 lis r0,RESET_VECTOR@h /* Address of reset vector */
452 ori r0,r0, RESET_VECTOR@l
453 stwu r1,-8(r1) /* Save back chain and move SP */
454 stw r0,+12(r1) /* Save return addr (underflow vect) */
463 /* --FIXME-- machine check with MCSRRn and rfmci */
465 .globl _start_of_vectors
468 /* Critical input. */
469 CRIT_EXCEPTION(0x0100, CritcalInput, CritcalInputException)
471 /* Machine check --FIXME-- Should be MACH_EXCEPTION */
472 CRIT_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
474 /* Data Storage exception. */
475 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
477 /* Instruction Storage exception. */
478 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
480 /* External Interrupt exception. */
481 STD_EXCEPTION(0x0500, ExtInterrupt, UnknownException)
483 /* Alignment exception. */
491 addi r3,r1,STACK_FRAME_OVERHEAD
493 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
494 lwz r6,GOT(transfer_to_handler)
498 .long AlignmentException - _start + EXC_OFF_SYS_RESET
499 .long int_return - _start + EXC_OFF_SYS_RESET
501 /* Program check exception */
505 addi r3,r1,STACK_FRAME_OVERHEAD
507 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
508 lwz r6,GOT(transfer_to_handler)
512 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
513 .long int_return - _start + EXC_OFF_SYS_RESET
515 /* No FPU on MPC85xx. This exception is not supposed to happen.
517 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
518 STD_EXCEPTION(0x0900, Decrementer, timer_interrupt)
519 STD_EXCEPTION(0x0a00, Trap_0a, UnknownException)
520 STD_EXCEPTION(0x0b00, Trap_0b, UnknownException)
524 * r0 - SYSCALL number
528 addis r11,r0,0 /* get functions table addr */
529 ori r11,r11,0 /* Note: this code is patched in trap_init */
530 addis r12,r0,0 /* get number of functions */
536 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
540 li r20,0xd00-4 /* Get stack pointer */
542 subi r12,r12,12 /* Adjust stack pointer */
543 li r0,0xc00+_end_back-SystemCall
544 cmplw 0, r0, r12 /* Check stack overflow */
555 li r12,0xc00+_back-SystemCall
563 mfmsr r11 /* Disable interrupts */
567 SYNC /* Some chip revs need this... */
571 li r12,0xd00-4 /* restore regs */
581 addi r12,r12,12 /* Adjust stack pointer */
589 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
591 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
592 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
594 STD_EXCEPTION(0x1000, PIT, PITException)
596 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
597 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
598 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
599 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
601 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
602 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
603 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
604 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
605 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
606 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
607 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
609 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
610 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
611 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
612 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
614 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
616 .globl _end_of_vectors
623 * This code finishes saving the registers to the exception frame
624 * and jumps to the appropriate handler for the exception.
625 * Register r21 is pointer into trap frame, r1 has new stack pointer.
627 .globl transfer_to_handler
639 andi. r24,r23,0x3f00 /* get vector offset */
643 mtspr SPRG2,r22 /* r1 is now kernel sp */
645 lwz r24,0(r23) /* virtual address of handler */
646 lwz r23,4(r23) /* where to go when done */
651 rfi /* jump to handler, enable MMU */
654 mfmsr r28 /* Disable interrupts */
658 SYNC /* Some chip revs need this... */
673 lwz r2,_NIP(r1) /* Restore environment */
684 mfmsr r28 /* Disable interrupts */
688 SYNC /* Some chip revs need this... */
703 lwz r2,_NIP(r1) /* Restore environment */
705 mtspr 990,r2 /* SRR2 */
706 mtspr 991,r0 /* SRR3 */
720 blr /* entire I cache */
744 .globl icache_disable
748 ori r1,r1,0xfffffffe@l
757 srwi r3, r3, 31 /* >>31 => select bit 0 */
775 .globl dcache_disable
779 ori r1,r1,0xfffffffe@l
790 srwi r3, r3, 31 /* >>31 => select bit 0 */
813 /*------------------------------------------------------------------------------- */
815 /* Description: Input 8 bits */
816 /*------------------------------------------------------------------------------- */
822 /*------------------------------------------------------------------------------- */
824 /* Description: Output 8 bits */
825 /*------------------------------------------------------------------------------- */
831 /*------------------------------------------------------------------------------- */
832 /* Function: out16 */
833 /* Description: Output 16 bits */
834 /*------------------------------------------------------------------------------- */
840 /*------------------------------------------------------------------------------- */
841 /* Function: out16r */
842 /* Description: Byte reverse and output 16 bits */
843 /*------------------------------------------------------------------------------- */
849 /*------------------------------------------------------------------------------- */
850 /* Function: out32 */
851 /* Description: Output 32 bits */
852 /*------------------------------------------------------------------------------- */
858 /*------------------------------------------------------------------------------- */
859 /* Function: out32r */
860 /* Description: Byte reverse and output 32 bits */
861 /*------------------------------------------------------------------------------- */
867 /*------------------------------------------------------------------------------- */
869 /* Description: Input 16 bits */
870 /*------------------------------------------------------------------------------- */
876 /*------------------------------------------------------------------------------- */
877 /* Function: in16r */
878 /* Description: Input 16 bits and byte reverse */
879 /*------------------------------------------------------------------------------- */
885 /*------------------------------------------------------------------------------- */
887 /* Description: Input 32 bits */
888 /*------------------------------------------------------------------------------- */
894 /*------------------------------------------------------------------------------- */
895 /* Function: in32r */
896 /* Description: Input 32 bits and byte reverse */
897 /*------------------------------------------------------------------------------- */
903 /*------------------------------------------------------------------------------- */
904 /* Function: ppcDcbf */
905 /* Description: Data Cache block flush */
906 /* Input: r3 = effective address */
908 /*------------------------------------------------------------------------------- */
914 /*------------------------------------------------------------------------------- */
915 /* Function: ppcDcbi */
916 /* Description: Data Cache block Invalidate */
917 /* Input: r3 = effective address */
919 /*------------------------------------------------------------------------------- */
925 /*------------------------------------------------------------------------------- */
926 /* Function: ppcSync */
927 /* Description: Processor Synchronize */
930 /*------------------------------------------------------------------------------- */
936 /*------------------------------------------------------------------------------*/
939 * void relocate_code (addr_sp, gd, addr_moni)
941 * This "function" does not return, instead it continues in RAM
942 * after relocating the monitor code.
946 * r5 = length in bytes
951 mr r1, r3 /* Set new stack pointer */
952 mr r9, r4 /* Save copy of Init Data pointer */
953 mr r10, r5 /* Save copy of Destination Address */
955 mr r3, r5 /* Destination Address */
956 lis r4, CFG_MONITOR_BASE@h /* Source Address */
957 ori r4, r4, CFG_MONITOR_BASE@l
958 lwz r5,GOT(__init_end)
960 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
965 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
971 /* First our own GOT */
973 /* the the one used by the C code */
983 beq cr1,4f /* In place copy is not necessary */
984 beq 7f /* Protect against 0 count */
1003 * Now flush the cache: note that we must start from a cache aligned
1004 * address. Otherwise we might miss one cache line.
1008 beq 7f /* Always flush prefetch queue in any case */
1016 sync /* Wait for all dcbst to complete on bus */
1022 7: sync /* Wait for all icbi to complete on bus */
1026 * We are done. Do not return, instead branch to second part of board
1027 * initialization, now running from RAM.
1030 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
1032 blr /* NEVER RETURNS! */
1037 * Relocation Function, r14 point to got2+0x8000
1039 * Adjust got2 pointers, no need to check for 0, this code
1040 * already puts a few entries in the table.
1042 li r0,__got2_entries@sectoff@l
1043 la r3,GOT(_GOT2_TABLE_)
1044 lwz r11,GOT(_GOT2_TABLE_)
1054 * Now adjust the fixups and the pointers to the fixups
1055 * in case we need to move ourselves again.
1057 2: li r0,__fixup_entries@sectoff@l
1058 lwz r3,GOT(_FIXUP_TABLE_)
1072 * Now clear BSS segment
1074 lwz r3,GOT(__bss_start)
1088 mr r3, r9 /* Init Data pointer */
1089 mr r4, r10 /* Destination Address */
1093 * Copy exception vector code to low memory
1096 * r7: source address, r8: end address, r9: target address
1101 lwz r8, GOT(_end_of_vectors)
1103 li r9, 0x100 /* reset vector always at 0x100 */
1106 bgelr /* return if r7>=r8 - just in case */
1108 mflr r4 /* save link register */
1118 * relocate `hdlr' and `int_return' entries
1120 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1121 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1124 addi r7, r7, 0x100 /* next exception vector */
1128 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1131 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1134 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1135 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1138 addi r7, r7, 0x100 /* next exception vector */
1142 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1143 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1146 addi r7, r7, 0x100 /* next exception vector */
1150 mtlr r4 /* restore link register */
1154 * Function: relocate entries for one exception vector
1157 lwz r0, 0(r7) /* hdlr ... */
1158 add r0, r0, r3 /* ... += dest_addr */
1161 lwz r0, 4(r7) /* int_return ... */
1162 add r0, r0, r3 /* ... += dest_addr */
1167 #ifdef CFG_INIT_RAM_LOCK
1168 .globl unlock_ram_in_cache
1169 unlock_ram_in_cache:
1170 /* invalidate the INIT_RAM section */
1171 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1172 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1179 sync /* Wait for all icbi to complete on bus */