2 * Copyright 2004 Freescale Semiconductor.
3 * Copyright (C) 2003 Motorola,Inc.
4 * Xianghua Xiao<X.Xiao@motorola.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
27 * The processor starts at 0xfffffffc and the code is first executed in the
28 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
36 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
44 #ifndef CONFIG_IDENT_STRING
45 #define CONFIG_IDENT_STRING ""
49 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
52 * Set up GOT: Global Offset Table
54 * Use r14 to access the GOT
57 GOT_ENTRY(_GOT2_TABLE_)
58 GOT_ENTRY(_FIXUP_TABLE_)
61 GOT_ENTRY(_start_of_vectors)
62 GOT_ENTRY(_end_of_vectors)
63 GOT_ENTRY(transfer_to_handler)
67 GOT_ENTRY(__bss_start)
71 * e500 Startup -- after reset only the last 4KB of the effective
72 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
73 * section is located at THIS LAST page and basically does three
74 * things: clear some registers, set up exception tables and
75 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
76 * continue the boot procedure.
78 * Once the boot rom is mapped by TLB entries we can proceed
79 * with normal startup.
88 lis r1, PVR_85xx_REV1@h
89 ori r1, r1, PVR_85xx_REV1@l
93 /* Semi-bogus errata fixup for Rev 1 */
98 * Before invalidating MMU L1/L2, read TLB1 Entry 0 and then
99 * write it back immediately to fixup a Rev 1 bug (Errata CPU4)
100 * for this initial TLB1 entry 0, otherwise the TLB1 entry 0
101 * will be invalidated (incorrectly).
111 * Clear and set up some registers.
112 * Note: Some registers need strict synchronization by
113 * sync/mbar/msync/isync when being "mtspr".
114 * BookE: isync before PID,tlbivax,tlbwe
115 * BookE: isync after MSR,PID; msync_isync after tlbivax & tlbwe
116 * E500: msync,isync before L1CSR0
117 * E500: isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1,
118 * L1CSR0, L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2],
122 /* invalidate d-cache */
130 /* disable d-cache */
134 /* invalidate i-cache */
140 /* disable i-cache */
145 /* clear registers */
167 mtspr DBSR,r1 /* Clear all valid bits */
174 mtspr BUCSR,r0 /* disable branch prediction */
179 /* Setup interrupt vectors */
184 mtspr IVOR0,r1 /* 0: Critical input */
186 mtspr IVOR1,r1 /* 1: Machine check */
188 mtspr IVOR2,r1 /* 2: Data storage */
190 mtspr IVOR3,r1 /* 3: Instruction storage */
192 mtspr IVOR4,r1 /* 4: External interrupt */
194 mtspr IVOR5,r1 /* 5: Alignment */
196 mtspr IVOR6,r1 /* 6: Program check */
198 mtspr IVOR7,r1 /* 7: floating point unavailable */
200 mtspr IVOR8,r1 /* 8: System call */
201 /* 9: Auxiliary processor unavailable(unsupported) */
203 mtspr IVOR10,r1 /* 10: Decrementer */
205 mtspr IVOR13,r1 /* 13: Data TLB error */
207 mtspr IVOR14,r1 /* 14: Instruction TLB error */
209 mtspr IVOR15,r1 /* 15: Debug */
212 * Invalidate MMU L1/L2
214 * Note: There is a fixup earlier for Errata CPU4 on
215 * Rev 1 parts that must precede this MMU invalidation.
222 * Invalidate all TLB0 entries.
228 * To avoid REV1 Errata CPU6 issues, make sure
229 * the instruction following tlbivax is not a store.
233 * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
234 * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
235 * region before we can access any CCSR registers such as L2
236 * registers, Local Access Registers,etc. We will also re-allocate
237 * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup.
239 * Please refer to board-specif directory for TLB1 entry configuration.
240 * (e.g. board/<yourboard>/init.S)
245 li r1,0x0020 /* max 16 TLB1 plus some TLB0 entries */
247 lwzu r4,0(r5) /* how many TLB1 entries we actually use */
267 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
268 /* Special sequence needed to update CCSRBAR itself */
269 lis r4, CFG_CCSRBAR_DEFAULT@h
270 ori r4, r4, CFG_CCSRBAR_DEFAULT@l
272 lis r5, CFG_CCSRBAR@h
273 ori r5, r5, CFG_CCSRBAR@l
283 lis r3, CFG_CCSRBAR@h
284 lwz r5, CFG_CCSRBAR@l(r3)
289 /* set up local access windows, defined at board/<boardname>/init.S */
291 ori r7,r7,CFG_CCSRBAR@l
295 li r1,0x0007 /* 8 LAWs, but reserve one for boot-over-rio-or-pci */
297 lwzu r5,0(r6) /* how many windows we actually use */
299 li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */
313 /* Jump out the last 4K page and continue to 'normal' start */
318 mtspr SRR1,r0 /* Keep things disabled for now */
324 * r3 - 1st arg to board_init(): IMMP pointer
325 * r4 - 2nd arg to board_init(): boot flag
328 .long 0x27051956 /* U-BOOT Magic Number */
329 .globl version_string
331 .ascii U_BOOT_VERSION
332 .ascii " (", __DATE__, " - ", __TIME__, ")"
333 .ascii CONFIG_IDENT_STRING, "\0"
335 . = EXC_OFF_SYS_RESET
338 /* Clear and set up some registers. */
341 mtspr DEC,r0 /* prevent dec exceptions */
342 mttbl r0 /* prevent fit & wdt exceptions */
344 mtspr TSR,r1 /* clear all timer exception status */
345 mtspr TCR,r0 /* disable all */
346 mtspr ESR,r0 /* clear exception syndrome register */
347 mtspr MCSR,r0 /* machine check syndrome register */
348 mtxer r0 /* clear integer exception register */
349 lis r1,0x0002 /* set CE bit (Critical Exceptions) */
350 ori r1,r1,0x1200 /* set ME/DE bit */
351 mtmsr r1 /* change MSR */
354 /* Enable Time Base and Select Time Base Clock */
355 lis r0,HID0_EMCP@h /* Enable machine check */
356 ori r0,r0,0x4000 /* time base is processor clock */
359 #if defined(CONFIG_ADDR_STREAMING)
366 /* Enable Branch Prediction */
367 #if defined(CONFIG_BTB)
368 li r0,0x201 /* BBFI = 1, BPEN = 1 */
372 #if defined(CFG_INIT_DBCR)
375 mtspr DBSR,r1 /* Clear all status bits */
376 lis r0,CFG_INIT_DBCR@h /* DBCR0[IDM] must be set */
377 ori r0,r0,CFG_INIT_DBCR@l
381 /* L1 DCache is used for initial RAM */
385 mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */
388 /* Allocate Initial RAM in data cache.
390 lis r3, CFG_INIT_RAM_ADDR@h
391 ori r3, r3, CFG_INIT_RAM_ADDR@l
392 li r2, 512 /* 512*32=16K */
402 /* Calculate absolute address in FLASH and jump there */
403 /*--------------------------------------------------------------*/
404 lis r3, CFG_MONITOR_BASE@h
405 ori r3, r3, CFG_MONITOR_BASE@l
406 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
411 #endif /* CFG_RAMBOOT */
413 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
414 lis r1,CFG_INIT_RAM_ADDR@h
415 ori r1,r1,CFG_INIT_SP_OFFSET@l
419 stwu r0,-4(r1) /* Terminate call chain */
421 stwu r1,-8(r1) /* Save back chain and move SP */
422 lis r0,RESET_VECTOR@h /* Address of reset vector */
423 ori r0,r0, RESET_VECTOR@l
424 stwu r1,-8(r1) /* Save back chain and move SP */
425 stw r0,+12(r1) /* Save return addr (underflow vect) */
433 /* --FIXME-- machine check with MCSRRn and rfmci */
435 .globl _start_of_vectors
438 /* Critical input. */
439 CRIT_EXCEPTION(0x0100, CritcalInput, CritcalInputException)
441 /* Machine check --FIXME-- Should be MACH_EXCEPTION */
442 CRIT_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
444 /* Data Storage exception. */
445 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
447 /* Instruction Storage exception. */
448 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
450 /* External Interrupt exception. */
451 STD_EXCEPTION(0x0500, ExtInterrupt, UnknownException)
453 /* Alignment exception. */
461 addi r3,r1,STACK_FRAME_OVERHEAD
463 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
464 lwz r6,GOT(transfer_to_handler)
468 .long AlignmentException - _start + EXC_OFF_SYS_RESET
469 .long int_return - _start + EXC_OFF_SYS_RESET
471 /* Program check exception */
475 addi r3,r1,STACK_FRAME_OVERHEAD
477 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
478 lwz r6,GOT(transfer_to_handler)
482 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
483 .long int_return - _start + EXC_OFF_SYS_RESET
485 /* No FPU on MPC85xx. This exception is not supposed to happen.
487 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
488 STD_EXCEPTION(0x0900, Decrementer, timer_interrupt)
489 STD_EXCEPTION(0x0a00, Trap_0a, UnknownException)
490 STD_EXCEPTION(0x0b00, Trap_0b, UnknownException)
494 * r0 - SYSCALL number
498 addis r11,r0,0 /* get functions table addr */
499 ori r11,r11,0 /* Note: this code is patched in trap_init */
500 addis r12,r0,0 /* get number of functions */
506 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
510 li r20,0xd00-4 /* Get stack pointer */
512 subi r12,r12,12 /* Adjust stack pointer */
513 li r0,0xc00+_end_back-SystemCall
514 cmplw 0, r0, r12 /* Check stack overflow */
525 li r12,0xc00+_back-SystemCall
533 mfmsr r11 /* Disable interrupts */
537 SYNC /* Some chip revs need this... */
541 li r12,0xd00-4 /* restore regs */
551 addi r12,r12,12 /* Adjust stack pointer */
559 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
561 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
562 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
564 STD_EXCEPTION(0x1000, PIT, PITException)
566 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
567 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
568 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
569 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
571 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
572 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
573 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
574 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
575 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
576 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
577 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
579 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
580 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
581 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
582 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
584 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
586 .globl _end_of_vectors
593 * This code finishes saving the registers to the exception frame
594 * and jumps to the appropriate handler for the exception.
595 * Register r21 is pointer into trap frame, r1 has new stack pointer.
597 .globl transfer_to_handler
609 andi. r24,r23,0x3f00 /* get vector offset */
613 mtspr SPRG2,r22 /* r1 is now kernel sp */
615 lwz r24,0(r23) /* virtual address of handler */
616 lwz r23,4(r23) /* where to go when done */
621 rfi /* jump to handler, enable MMU */
624 mfmsr r28 /* Disable interrupts */
628 SYNC /* Some chip revs need this... */
643 lwz r2,_NIP(r1) /* Restore environment */
654 mfmsr r28 /* Disable interrupts */
658 SYNC /* Some chip revs need this... */
673 lwz r2,_NIP(r1) /* Restore environment */
675 mtspr 990,r2 /* SRR2 */
676 mtspr 991,r0 /* SRR3 */
690 blr /* entire I cache */
714 .globl icache_disable
718 ori r1,r1,0xfffffffe@l
727 srwi r3, r3, 31 /* >>31 => select bit 0 */
745 .globl dcache_disable
749 ori r1,r1,0xfffffffe@l
760 srwi r3, r3, 31 /* >>31 => select bit 0 */
783 /*------------------------------------------------------------------------------- */
785 /* Description: Input 8 bits */
786 /*------------------------------------------------------------------------------- */
792 /*------------------------------------------------------------------------------- */
794 /* Description: Output 8 bits */
795 /*------------------------------------------------------------------------------- */
801 /*------------------------------------------------------------------------------- */
802 /* Function: out16 */
803 /* Description: Output 16 bits */
804 /*------------------------------------------------------------------------------- */
810 /*------------------------------------------------------------------------------- */
811 /* Function: out16r */
812 /* Description: Byte reverse and output 16 bits */
813 /*------------------------------------------------------------------------------- */
819 /*------------------------------------------------------------------------------- */
820 /* Function: out32 */
821 /* Description: Output 32 bits */
822 /*------------------------------------------------------------------------------- */
828 /*------------------------------------------------------------------------------- */
829 /* Function: out32r */
830 /* Description: Byte reverse and output 32 bits */
831 /*------------------------------------------------------------------------------- */
837 /*------------------------------------------------------------------------------- */
839 /* Description: Input 16 bits */
840 /*------------------------------------------------------------------------------- */
846 /*------------------------------------------------------------------------------- */
847 /* Function: in16r */
848 /* Description: Input 16 bits and byte reverse */
849 /*------------------------------------------------------------------------------- */
855 /*------------------------------------------------------------------------------- */
857 /* Description: Input 32 bits */
858 /*------------------------------------------------------------------------------- */
864 /*------------------------------------------------------------------------------- */
865 /* Function: in32r */
866 /* Description: Input 32 bits and byte reverse */
867 /*------------------------------------------------------------------------------- */
873 /*------------------------------------------------------------------------------- */
874 /* Function: ppcDcbf */
875 /* Description: Data Cache block flush */
876 /* Input: r3 = effective address */
878 /*------------------------------------------------------------------------------- */
884 /*------------------------------------------------------------------------------- */
885 /* Function: ppcDcbi */
886 /* Description: Data Cache block Invalidate */
887 /* Input: r3 = effective address */
889 /*------------------------------------------------------------------------------- */
895 /*--------------------------------------------------------------------------
897 * Description: Data Cache block zero.
898 * Input: r3 = effective address
900 *-------------------------------------------------------------------------- */
907 /*------------------------------------------------------------------------------- */
908 /* Function: ppcSync */
909 /* Description: Processor Synchronize */
912 /*------------------------------------------------------------------------------- */
918 /*------------------------------------------------------------------------------*/
921 * void relocate_code (addr_sp, gd, addr_moni)
923 * This "function" does not return, instead it continues in RAM
924 * after relocating the monitor code.
928 * r5 = length in bytes
933 mr r1, r3 /* Set new stack pointer */
934 mr r9, r4 /* Save copy of Init Data pointer */
935 mr r10, r5 /* Save copy of Destination Address */
937 mr r3, r5 /* Destination Address */
938 lis r4, CFG_MONITOR_BASE@h /* Source Address */
939 ori r4, r4, CFG_MONITOR_BASE@l
940 lwz r5,GOT(__init_end)
942 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
947 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
953 /* First our own GOT */
955 /* the the one used by the C code */
965 beq cr1,4f /* In place copy is not necessary */
966 beq 7f /* Protect against 0 count */
985 * Now flush the cache: note that we must start from a cache aligned
986 * address. Otherwise we might miss one cache line.
990 beq 7f /* Always flush prefetch queue in any case */
998 sync /* Wait for all dcbst to complete on bus */
1004 7: sync /* Wait for all icbi to complete on bus */
1008 * We are done. Do not return, instead branch to second part of board
1009 * initialization, now running from RAM.
1012 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
1014 blr /* NEVER RETURNS! */
1019 * Relocation Function, r14 point to got2+0x8000
1021 * Adjust got2 pointers, no need to check for 0, this code
1022 * already puts a few entries in the table.
1024 li r0,__got2_entries@sectoff@l
1025 la r3,GOT(_GOT2_TABLE_)
1026 lwz r11,GOT(_GOT2_TABLE_)
1036 * Now adjust the fixups and the pointers to the fixups
1037 * in case we need to move ourselves again.
1039 2: li r0,__fixup_entries@sectoff@l
1040 lwz r3,GOT(_FIXUP_TABLE_)
1054 * Now clear BSS segment
1056 lwz r3,GOT(__bss_start)
1070 mr r3, r9 /* Init Data pointer */
1071 mr r4, r10 /* Destination Address */
1075 * Copy exception vector code to low memory
1078 * r7: source address, r8: end address, r9: target address
1083 lwz r8, GOT(_end_of_vectors)
1085 li r9, 0x100 /* reset vector always at 0x100 */
1088 bgelr /* return if r7>=r8 - just in case */
1090 mflr r4 /* save link register */
1100 * relocate `hdlr' and `int_return' entries
1102 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1103 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1106 addi r7, r7, 0x100 /* next exception vector */
1110 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1113 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1116 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1117 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1120 addi r7, r7, 0x100 /* next exception vector */
1124 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1125 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1128 addi r7, r7, 0x100 /* next exception vector */
1132 mtlr r4 /* restore link register */
1136 * Function: relocate entries for one exception vector
1139 lwz r0, 0(r7) /* hdlr ... */
1140 add r0, r0, r3 /* ... += dest_addr */
1143 lwz r0, 4(r7) /* int_return ... */
1144 add r0, r0, r3 /* ... += dest_addr */
1149 #ifdef CFG_INIT_RAM_LOCK
1150 .globl unlock_ram_in_cache
1151 unlock_ram_in_cache:
1152 /* invalidate the INIT_RAM section */
1153 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1154 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1161 sync /* Wait for all icbi to complete on bus */