2 * Copyright (C) 2003 Motorola,Inc.
3 * Xianghua Xiao<X.Xiao@motorola.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
35 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
37 #include <ppc_asm.tmpl>
40 #include <asm/cache.h>
43 #ifndef CONFIG_IDENT_STRING
44 #define CONFIG_IDENT_STRING ""
48 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
51 * Set up GOT: Global Offset Table
53 * Use r14 to access the GOT
56 GOT_ENTRY(_GOT2_TABLE_)
57 GOT_ENTRY(_FIXUP_TABLE_)
60 GOT_ENTRY(_start_of_vectors)
61 GOT_ENTRY(_end_of_vectors)
62 GOT_ENTRY(transfer_to_handler)
66 GOT_ENTRY(__bss_start)
70 * e500 Startup -- after reset only the last 4KB of the effective
71 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
72 * section is located at THIS LAST page and basically does three
73 * things: clear some registers, set up exception tables and
74 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
75 * continue the boot procedure.
77 * Once the boot rom is mapped by TLB entries we can proceed
78 * with normal startup.
86 #if defined(CONFIG_MPC85xx_REV1)
91 /* Clear and set up some registers. Note: Some registers need strict
92 * synchronization by sync/mbar/msync/isync when being "mtspr".
93 * BookE: isync before PID,tlbivax,tlbwe
94 * BookE: isync after MSR,PID; msync_isync after tlbivax & tlbwe
95 * E500: msync,isync before L1CSR0
96 * E500: isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1,L1CSR0
97 * L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2],SPEFCSR
100 /* invalidate d-cache */
108 /* disable d-cache */
113 /* invalidate i-cache */
119 /* disable i-cache */
124 /* clear registers */
150 mtspr DBSR,r1 /* Clear all valid bits */
162 mtspr BUCSR,r0 /* disable branch prediction */
175 /* Setup interrupt vectors */
179 mtspr IVOR0,r1 /* 0: Critical input */
181 mtspr IVOR1,r1 /* 1: Machine check */
183 mtspr IVOR2,r1 /* 2: Data storage */
185 mtspr IVOR3,r1 /* 3: Instruction storage */
187 mtspr IVOR4,r1 /* 4: External interrupt */
189 mtspr IVOR5,r1 /* 5: Alignment */
191 mtspr IVOR6,r1 /* 6: Program check */
193 mtspr IVOR7,r1 /* 7: floating point unavailable */
195 mtspr IVOR8,r1 /* 8: System call */
196 /* 9: Auxiliary processor unavailable(unsupported) */
198 mtspr IVOR10,r1 /* 10: Decrementer */
200 mtspr IVOR13,r1 /* 13: Data TLB error */
202 mtspr IVOR14,r1 /* 14: Instruction TLB error */
204 mtspr IVOR15,r1 /* 15: Debug */
206 /* invalidate MMU L1/L2 */
207 /* Note: before invalidate MMU L1/L2, we read TLB1 Entry 0 and then
208 * write it back immediately to fixup a bug(Errata CPU4) for this initial
209 * TLB1 entry 0,otherwise the TLB1 entry 0 will be invalidated.
211 #if defined(CONFIG_MPC85xx_REV1)
222 /* After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
223 * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
224 * region before we can access any CCSR registers such as L2
225 * registers, Local Access Registers,etc. We will also re-allocate
226 * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup.
228 * Please refer to board-specif directory for TLB1 entry configuration.
229 * (e.g. board/<yourboard>/init.S)
234 li r1,0x000f /* max 16 TLB1 entries */
236 lwzu r4,0(r5) /* how many TLB1 entries we actually use */
256 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
257 /* Special sequence needed to update CCSRBAR itself */
258 lis r4, CFG_CCSRBAR_DEFAULT@h
259 ori r4, r4, CFG_CCSRBAR_DEFAULT@l
261 lis r5, CFG_CCSRBAR@h
262 ori r5, r5, CFG_CCSRBAR@l
272 lis r3, CFG_CCSRBAR@h
273 lwz r5, CFG_CCSRBAR@l(r3)
277 /* invalidate all TLB0 entries */
281 #if defined(CONFIG_MPC85xx_REV1) /* Errata CPU6 */
285 /* set up local access windows, defined at board/<boardname>/init.S */
287 ori r7,r7,CFG_CCSRBAR@l
291 #if defined(CONFIG_RAM_AS_FLASH)
294 li r1,0x0007 /*we have 8 LAWs, but reseve one for boot-over-rio-or-pci */
297 lwzu r5,0(r6) /* how many windows we actually use */
299 #if defined(CONFIG_RAM_AS_FLASH)
303 li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */
318 /* Jump out the last 4K page and continue to 'normal' start */
323 mtspr SRR1,r0 /* Keep things disabled for now */
329 * r3 - 1st arg to board_init(): IMMP pointer
330 * r4 - 2nd arg to board_init(): boot flag
333 .long 0x27051956 /* U-BOOT Magic Number */
334 .globl version_string
336 .ascii U_BOOT_VERSION
337 .ascii " (", __DATE__, " - ", __TIME__, ")"
338 .ascii CONFIG_IDENT_STRING, "\0"
340 . = EXC_OFF_SYS_RESET
343 /* Clear and set up some registers. */
346 mtspr DEC,r0 /* prevent dec exceptions */
347 mttbl r0 /* prevent fit & wdt exceptions */
349 mtspr TSR,r1 /* clear all timer exception status */
350 mtspr TCR,r0 /* disable all */
351 mtspr ESR,r0 /* clear exception syndrome register */
352 mtspr MCSR,r0 /* machine check syndrome register */
353 mtxer r0 /* clear integer exception register */
354 lis r1,0x0002 /* set CE bit (Critical Exceptions) */
355 ori r1,r1,0x1200 /* set ME/DE bit */
356 mtmsr r1 /* change MSR */
359 /* Enable Time Base and Select Time Base Clock */
360 li r0,0x4000 /* time base is processor clock */
364 #if defined(CONFIG_ADDR_STREAMING)
372 /* Enable Branch Prediction */
373 #if defined(CONFIG_BTB)
374 li r0,0x201 /* BBFI = 1, BPEN = 1 */
379 #if defined(CFG_INIT_DBCR)
382 mtspr dbsr,r1 /* Clear all status bits */
383 lis r0,CFG_INIT_DBCR@h /* DBCR0[IDM] must be set */
384 ori r0,r0,CFG_INIT_DBCR@l
389 /* L1 DCache is used for initial RAM */
395 mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */
398 /* Allocate Initial RAM in data cache.
400 lis r3, CFG_INIT_RAM_ADDR@h
401 ori r3, r3, CFG_INIT_RAM_ADDR@l
402 li r2, 512 /* 512*32=16K */
412 /* Calculate absolute address in FLASH and jump there */
413 /*--------------------------------------------------------------*/
414 lis r3, CFG_MONITOR_BASE@h
415 ori r3, r3, CFG_MONITOR_BASE@l
416 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
421 #endif /* CFG_RAMBOOT */
423 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
424 lis r1,CFG_INIT_RAM_ADDR@h
425 ori r1,r1,CFG_INIT_SP_OFFSET@l
429 stwu r0,-4(r1) /* Terminate call chain */
431 stwu r1,-8(r1) /* Save back chain and move SP */
432 lis r0,RESET_VECTOR@h /* Address of reset vector */
433 ori r0,r0, RESET_VECTOR@l
434 stwu r1,-8(r1) /* Save back chain and move SP */
435 stw r0,+12(r1) /* Save return addr (underflow vect) */
444 /* --FIXME-- machine check with MCSRRn and rfmci */
446 .globl _start_of_vectors
449 /* Critical input. */
450 CRIT_EXCEPTION(0x0100, CritcalInput, CritcalInputException)
452 /* Machine check --FIXME-- Should be MACH_EXCEPTION */
453 CRIT_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
455 /* Data Storage exception. */
456 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
458 /* Instruction Storage exception. */
459 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
461 /* External Interrupt exception. */
462 STD_EXCEPTION(0x0500, ExtInterrupt, UnknownException)
464 /* Alignment exception. */
472 addi r3,r1,STACK_FRAME_OVERHEAD
474 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
475 lwz r6,GOT(transfer_to_handler)
479 .long AlignmentException - _start + EXC_OFF_SYS_RESET
480 .long int_return - _start + EXC_OFF_SYS_RESET
482 /* Program check exception */
486 addi r3,r1,STACK_FRAME_OVERHEAD
488 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
489 lwz r6,GOT(transfer_to_handler)
493 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
494 .long int_return - _start + EXC_OFF_SYS_RESET
496 /* No FPU on MPC85xx. This exception is not supposed to happen.
498 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
499 STD_EXCEPTION(0x0900, Decrementer, timer_interrupt)
500 STD_EXCEPTION(0x0a00, Trap_0a, UnknownException)
501 STD_EXCEPTION(0x0b00, Trap_0b, UnknownException)
505 * r0 - SYSCALL number
509 addis r11,r0,0 /* get functions table addr */
510 ori r11,r11,0 /* Note: this code is patched in trap_init */
511 addis r12,r0,0 /* get number of functions */
517 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
521 li r20,0xd00-4 /* Get stack pointer */
523 subi r12,r12,12 /* Adjust stack pointer */
524 li r0,0xc00+_end_back-SystemCall
525 cmplw 0, r0, r12 /* Check stack overflow */
536 li r12,0xc00+_back-SystemCall
544 mfmsr r11 /* Disable interrupts */
548 SYNC /* Some chip revs need this... */
552 li r12,0xd00-4 /* restore regs */
562 addi r12,r12,12 /* Adjust stack pointer */
570 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
572 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
573 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
575 STD_EXCEPTION(0x1000, PIT, PITException)
577 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
578 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
579 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
580 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
582 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
583 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
584 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
585 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
586 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
587 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
588 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
590 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
591 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
592 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
593 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
595 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
597 .globl _end_of_vectors
604 * This code finishes saving the registers to the exception frame
605 * and jumps to the appropriate handler for the exception.
606 * Register r21 is pointer into trap frame, r1 has new stack pointer.
608 .globl transfer_to_handler
620 andi. r24,r23,0x3f00 /* get vector offset */
624 mtspr SPRG2,r22 /* r1 is now kernel sp */
626 lwz r24,0(r23) /* virtual address of handler */
627 lwz r23,4(r23) /* where to go when done */
632 rfi /* jump to handler, enable MMU */
635 mfmsr r28 /* Disable interrupts */
639 SYNC /* Some chip revs need this... */
654 lwz r2,_NIP(r1) /* Restore environment */
665 mfmsr r28 /* Disable interrupts */
669 SYNC /* Some chip revs need this... */
684 lwz r2,_NIP(r1) /* Restore environment */
686 mtspr 990,r2 /* SRR2 */
687 mtspr 991,r0 /* SRR3 */
701 blr /* entire I cache */
725 .globl icache_disable
729 ori r1,r1,0xfffffffe@l
738 srwi r3, r3, 31 /* >>31 => select bit 0 */
756 .globl dcache_disable
760 ori r1,r1,0xfffffffe@l
771 srwi r3, r3, 31 /* >>31 => select bit 0 */
789 /*------------------------------------------------------------------------------- */
791 /* Description: Input 8 bits */
792 /*------------------------------------------------------------------------------- */
798 /*------------------------------------------------------------------------------- */
800 /* Description: Output 8 bits */
801 /*------------------------------------------------------------------------------- */
807 /*------------------------------------------------------------------------------- */
808 /* Function: out16 */
809 /* Description: Output 16 bits */
810 /*------------------------------------------------------------------------------- */
816 /*------------------------------------------------------------------------------- */
817 /* Function: out16r */
818 /* Description: Byte reverse and output 16 bits */
819 /*------------------------------------------------------------------------------- */
825 /*------------------------------------------------------------------------------- */
826 /* Function: out32 */
827 /* Description: Output 32 bits */
828 /*------------------------------------------------------------------------------- */
834 /*------------------------------------------------------------------------------- */
835 /* Function: out32r */
836 /* Description: Byte reverse and output 32 bits */
837 /*------------------------------------------------------------------------------- */
843 /*------------------------------------------------------------------------------- */
845 /* Description: Input 16 bits */
846 /*------------------------------------------------------------------------------- */
852 /*------------------------------------------------------------------------------- */
853 /* Function: in16r */
854 /* Description: Input 16 bits and byte reverse */
855 /*------------------------------------------------------------------------------- */
861 /*------------------------------------------------------------------------------- */
863 /* Description: Input 32 bits */
864 /*------------------------------------------------------------------------------- */
870 /*------------------------------------------------------------------------------- */
871 /* Function: in32r */
872 /* Description: Input 32 bits and byte reverse */
873 /*------------------------------------------------------------------------------- */
879 /*------------------------------------------------------------------------------- */
880 /* Function: ppcDcbf */
881 /* Description: Data Cache block flush */
882 /* Input: r3 = effective address */
884 /*------------------------------------------------------------------------------- */
890 /*------------------------------------------------------------------------------- */
891 /* Function: ppcDcbi */
892 /* Description: Data Cache block Invalidate */
893 /* Input: r3 = effective address */
895 /*------------------------------------------------------------------------------- */
901 /*------------------------------------------------------------------------------- */
902 /* Function: ppcSync */
903 /* Description: Processor Synchronize */
906 /*------------------------------------------------------------------------------- */
912 /*------------------------------------------------------------------------------*/
915 * void relocate_code (addr_sp, gd, addr_moni)
917 * This "function" does not return, instead it continues in RAM
918 * after relocating the monitor code.
922 * r5 = length in bytes
927 mr r1, r3 /* Set new stack pointer */
928 mr r9, r4 /* Save copy of Init Data pointer */
929 mr r10, r5 /* Save copy of Destination Address */
931 mr r3, r5 /* Destination Address */
932 lis r4, CFG_MONITOR_BASE@h /* Source Address */
933 ori r4, r4, CFG_MONITOR_BASE@l
934 lwz r5,GOT(__init_end)
936 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
941 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
947 /* First our own GOT */
949 /* the the one used by the C code */
959 beq cr1,4f /* In place copy is not necessary */
960 beq 7f /* Protect against 0 count */
979 * Now flush the cache: note that we must start from a cache aligned
980 * address. Otherwise we might miss one cache line.
984 beq 7f /* Always flush prefetch queue in any case */
992 sync /* Wait for all dcbst to complete on bus */
998 7: sync /* Wait for all icbi to complete on bus */
1002 * We are done. Do not return, instead branch to second part of board
1003 * initialization, now running from RAM.
1006 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
1008 blr /* NEVER RETURNS! */
1013 * Relocation Function, r14 point to got2+0x8000
1015 * Adjust got2 pointers, no need to check for 0, this code
1016 * already puts a few entries in the table.
1018 li r0,__got2_entries@sectoff@l
1019 la r3,GOT(_GOT2_TABLE_)
1020 lwz r11,GOT(_GOT2_TABLE_)
1030 * Now adjust the fixups and the pointers to the fixups
1031 * in case we need to move ourselves again.
1033 2: li r0,__fixup_entries@sectoff@l
1034 lwz r3,GOT(_FIXUP_TABLE_)
1048 * Now clear BSS segment
1050 lwz r3,GOT(__bss_start)
1064 mr r3, r9 /* Init Data pointer */
1065 mr r4, r10 /* Destination Address */
1069 * Copy exception vector code to low memory
1072 * r7: source address, r8: end address, r9: target address
1077 lwz r8, GOT(_end_of_vectors)
1079 li r9, 0x100 /* reset vector always at 0x100 */
1082 bgelr /* return if r7>=r8 - just in case */
1084 mflr r4 /* save link register */
1094 * relocate `hdlr' and `int_return' entries
1096 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1097 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1100 addi r7, r7, 0x100 /* next exception vector */
1104 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1107 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1110 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1111 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1114 addi r7, r7, 0x100 /* next exception vector */
1118 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1119 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1122 addi r7, r7, 0x100 /* next exception vector */
1126 mtlr r4 /* restore link register */
1130 * Function: relocate entries for one exception vector
1133 lwz r0, 0(r7) /* hdlr ... */
1134 add r0, r0, r3 /* ... += dest_addr */
1137 lwz r0, 4(r7) /* int_return ... */
1138 add r0, r0, r3 /* ... += dest_addr */
1143 #ifdef CFG_INIT_RAM_LOCK
1144 .globl unlock_ram_in_cache
1145 unlock_ram_in_cache:
1146 /* invalidate the INIT_RAM section */
1147 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1148 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1155 sync /* Wait for all icbi to complete on bus */