2 * Copyright 2004, 2007-2009 Freescale Semiconductor.
3 * Copyright (C) 2003 Motorola,Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
33 #include <timestamp.h>
36 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
44 #ifndef CONFIG_IDENT_STRING
45 #define CONFIG_IDENT_STRING ""
49 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
52 * Set up GOT: Global Offset Table
54 * Use r14 to access the GOT
57 GOT_ENTRY(_GOT2_TABLE_)
58 GOT_ENTRY(_FIXUP_TABLE_)
61 GOT_ENTRY(_start_of_vectors)
62 GOT_ENTRY(_end_of_vectors)
63 GOT_ENTRY(transfer_to_handler)
67 GOT_ENTRY(__bss_start)
71 * e500 Startup -- after reset only the last 4KB of the effective
72 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
73 * section is located at THIS LAST page and basically does three
74 * things: clear some registers, set up exception tables and
75 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
76 * continue the boot procedure.
78 * Once the boot rom is mapped by TLB entries we can proceed
79 * with normal startup.
88 /* clear registers/arrays not reset by hardware */
92 mtspr L1CSR0,r0 /* invalidate d-cache */
93 mtspr L1CSR1,r0 /* invalidate i-cache */
96 mtspr DBSR,r1 /* Clear all valid bits */
99 * Enable L1 Caches early
103 lis r2,L1CSR0_CPE@H /* enable parity */
105 mtspr L1CSR0,r2 /* enable L1 Dcache */
107 mtspr L1CSR1,r2 /* enable L1 Icache */
111 /* Setup interrupt vectors */
116 mtspr IVOR0,r1 /* 0: Critical input */
118 mtspr IVOR1,r1 /* 1: Machine check */
120 mtspr IVOR2,r1 /* 2: Data storage */
122 mtspr IVOR3,r1 /* 3: Instruction storage */
124 mtspr IVOR4,r1 /* 4: External interrupt */
126 mtspr IVOR5,r1 /* 5: Alignment */
128 mtspr IVOR6,r1 /* 6: Program check */
130 mtspr IVOR7,r1 /* 7: floating point unavailable */
132 mtspr IVOR8,r1 /* 8: System call */
133 /* 9: Auxiliary processor unavailable(unsupported) */
135 mtspr IVOR10,r1 /* 10: Decrementer */
137 mtspr IVOR11,r1 /* 11: Interval timer */
139 mtspr IVOR12,r1 /* 12: Watchdog timer */
141 mtspr IVOR13,r1 /* 13: Data TLB error */
143 mtspr IVOR14,r1 /* 14: Instruction TLB error */
145 mtspr IVOR15,r1 /* 15: Debug */
147 /* Clear and set up some registers. */
150 mtspr DEC,r0 /* prevent dec exceptions */
151 mttbl r0 /* prevent fit & wdt exceptions */
153 mtspr TSR,r1 /* clear all timer exception status */
154 mtspr TCR,r0 /* disable all */
155 mtspr ESR,r0 /* clear exception syndrome register */
156 mtspr MCSR,r0 /* machine check syndrome register */
157 mtxer r0 /* clear integer exception register */
159 #ifdef CONFIG_SYS_BOOK3E_HV
160 mtspr MAS8,r0 /* make sure MAS8 is clear */
163 /* Enable Time Base and Select Time Base Clock */
164 lis r0,HID0_EMCP@h /* Enable machine check */
165 #if defined(CONFIG_ENABLE_36BIT_PHYS)
166 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
168 #ifndef CONFIG_E500MC
169 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
173 #ifndef CONFIG_E500MC
174 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
178 /* Enable Branch Prediction */
179 #if defined(CONFIG_BTB)
180 li r0,0x201 /* BBFI = 1, BPEN = 1 */
184 #if defined(CONFIG_SYS_INIT_DBCR)
187 mtspr DBSR,r1 /* Clear all status bits */
188 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
189 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
193 #ifdef CONFIG_MPC8569
194 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
195 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
197 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
198 * use address space which is more than 12bits, and it must be done in
199 * the 4K boot page. So we set this bit here.
202 /* create a temp mapping TLB0[0] for LBCR */
203 lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h
204 ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
206 lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
207 ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
209 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
210 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
212 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
213 (MAS3_SX|MAS3_SW|MAS3_SR))@h
214 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
215 (MAS3_SX|MAS3_SW|MAS3_SR))@l
225 /* Set LBCR register */
226 lis r4,CONFIG_SYS_LBCR_ADDR@h
227 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
229 lis r5,CONFIG_SYS_LBC_LBCR@h
230 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
234 /* invalidate this temp TLB */
235 lis r4,CONFIG_SYS_LBC_ADDR@h
236 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
240 #endif /* CONFIG_MPC8569 */
242 /* create a temp mapping in AS=1 to the 4M boot window */
243 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
244 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
246 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
247 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
249 lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
250 ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
252 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
253 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
254 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
264 /* create a temp mapping in AS=1 to the stack */
265 lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
266 ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
268 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
269 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
271 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
272 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
274 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
275 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
285 lis r6,MSR_IS|MSR_DS@h
286 ori r6,r6,MSR_IS|MSR_DS@l
288 ori r7,r7,switch_as@l
295 /* L1 DCache is used for initial RAM */
297 /* Allocate Initial RAM in data cache.
299 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
300 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
303 /* cache size * 1024 / (2 * L1 line size) */
304 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
310 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
313 /* Jump out the last 4K page and continue to 'normal' start */
314 #ifdef CONFIG_SYS_RAMBOOT
317 /* Calculate absolute address in FLASH and jump there */
318 /*--------------------------------------------------------------*/
319 lis r3,CONFIG_SYS_MONITOR_BASE@h
320 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
321 addi r3,r3,_start_cont - _start + _START_OFFSET
329 .long 0x27051956 /* U-BOOT Magic Number */
330 .globl version_string
332 .ascii U_BOOT_VERSION
333 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
334 .ascii CONFIG_IDENT_STRING, "\0"
339 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
340 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
341 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
345 stwu r0,-4(r1) /* Terminate call chain */
347 stwu r1,-8(r1) /* Save back chain and move SP */
348 lis r0,RESET_VECTOR@h /* Address of reset vector */
349 ori r0,r0,RESET_VECTOR@l
350 stwu r1,-8(r1) /* Save back chain and move SP */
351 stw r0,+12(r1) /* Save return addr (underflow vect) */
356 /* switch back to AS = 0 */
357 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
358 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
366 . = EXC_OFF_SYS_RESET
367 .globl _start_of_vectors
370 /* Critical input. */
371 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
374 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
376 /* Data Storage exception. */
377 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
379 /* Instruction Storage exception. */
380 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
382 /* External Interrupt exception. */
383 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
385 /* Alignment exception. */
388 EXCEPTION_PROLOG(SRR0, SRR1)
393 addi r3,r1,STACK_FRAME_OVERHEAD
395 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
396 lwz r6,GOT(transfer_to_handler)
400 .long AlignmentException - _start + _START_OFFSET
401 .long int_return - _start + _START_OFFSET
403 /* Program check exception */
406 EXCEPTION_PROLOG(SRR0, SRR1)
407 addi r3,r1,STACK_FRAME_OVERHEAD
409 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
410 lwz r6,GOT(transfer_to_handler)
414 .long ProgramCheckException - _start + _START_OFFSET
415 .long int_return - _start + _START_OFFSET
417 /* No FPU on MPC85xx. This exception is not supposed to happen.
419 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
423 * r0 - SYSCALL number
427 addis r11,r0,0 /* get functions table addr */
428 ori r11,r11,0 /* Note: this code is patched in trap_init */
429 addis r12,r0,0 /* get number of functions */
435 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
439 li r20,0xd00-4 /* Get stack pointer */
441 subi r12,r12,12 /* Adjust stack pointer */
442 li r0,0xc00+_end_back-SystemCall
443 cmplw 0,r0,r12 /* Check stack overflow */
454 li r12,0xc00+_back-SystemCall
462 mfmsr r11 /* Disable interrupts */
466 SYNC /* Some chip revs need this... */
470 li r12,0xd00-4 /* restore regs */
480 addi r12,r12,12 /* Adjust stack pointer */
488 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
489 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
490 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
492 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
493 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
495 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
497 .globl _end_of_vectors
501 . = . + (0x100 - ( . & 0xff )) /* align for debug */
504 * This code finishes saving the registers to the exception frame
505 * and jumps to the appropriate handler for the exception.
506 * Register r21 is pointer into trap frame, r1 has new stack pointer.
508 .globl transfer_to_handler
520 andi. r24,r23,0x3f00 /* get vector offset */
524 mtspr SPRG2,r22 /* r1 is now kernel sp */
526 lwz r24,0(r23) /* virtual address of handler */
527 lwz r23,4(r23) /* where to go when done */
532 rfi /* jump to handler, enable MMU */
535 mfmsr r28 /* Disable interrupts */
539 SYNC /* Some chip revs need this... */
554 lwz r2,_NIP(r1) /* Restore environment */
565 mfmsr r28 /* Disable interrupts */
569 SYNC /* Some chip revs need this... */
584 lwz r2,_NIP(r1) /* Restore environment */
595 mfmsr r28 /* Disable interrupts */
599 SYNC /* Some chip revs need this... */
614 lwz r2,_NIP(r1) /* Restore environment */
626 .globl invalidate_icache
629 ori r0,r0,L1CSR1_ICFI
634 blr /* entire I cache */
636 .globl invalidate_dcache
639 ori r0,r0,L1CSR0_DCFI
659 .globl icache_disable
672 andi. r3,r3,L1CSR1_ICE
690 .globl dcache_disable
703 andi. r3,r3,L1CSR0_DCE
726 /*------------------------------------------------------------------------------- */
728 /* Description: Input 8 bits */
729 /*------------------------------------------------------------------------------- */
735 /*------------------------------------------------------------------------------- */
737 /* Description: Output 8 bits */
738 /*------------------------------------------------------------------------------- */
745 /*------------------------------------------------------------------------------- */
746 /* Function: out16 */
747 /* Description: Output 16 bits */
748 /*------------------------------------------------------------------------------- */
755 /*------------------------------------------------------------------------------- */
756 /* Function: out16r */
757 /* Description: Byte reverse and output 16 bits */
758 /*------------------------------------------------------------------------------- */
765 /*------------------------------------------------------------------------------- */
766 /* Function: out32 */
767 /* Description: Output 32 bits */
768 /*------------------------------------------------------------------------------- */
775 /*------------------------------------------------------------------------------- */
776 /* Function: out32r */
777 /* Description: Byte reverse and output 32 bits */
778 /*------------------------------------------------------------------------------- */
785 /*------------------------------------------------------------------------------- */
787 /* Description: Input 16 bits */
788 /*------------------------------------------------------------------------------- */
794 /*------------------------------------------------------------------------------- */
795 /* Function: in16r */
796 /* Description: Input 16 bits and byte reverse */
797 /*------------------------------------------------------------------------------- */
803 /*------------------------------------------------------------------------------- */
805 /* Description: Input 32 bits */
806 /*------------------------------------------------------------------------------- */
812 /*------------------------------------------------------------------------------- */
813 /* Function: in32r */
814 /* Description: Input 32 bits and byte reverse */
815 /*------------------------------------------------------------------------------- */
821 /*------------------------------------------------------------------------------*/
824 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
832 #ifdef CONFIG_ENABLE_36BIT_PHYS
836 #ifdef CONFIG_SYS_BOOK3E_HV
846 * void relocate_code (addr_sp, gd, addr_moni)
848 * This "function" does not return, instead it continues in RAM
849 * after relocating the monitor code.
853 * r5 = length in bytes
858 mr r1,r3 /* Set new stack pointer */
859 mr r9,r4 /* Save copy of Init Data pointer */
860 mr r10,r5 /* Save copy of Destination Address */
862 mr r3,r5 /* Destination Address */
863 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
864 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
865 lwz r5,GOT(__init_end)
867 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
872 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
878 /* First our own GOT */
880 /* the the one used by the C code */
890 beq cr1,4f /* In place copy is not necessary */
891 beq 7f /* Protect against 0 count */
910 * Now flush the cache: note that we must start from a cache aligned
911 * address. Otherwise we might miss one cache line.
915 beq 7f /* Always flush prefetch queue in any case */
923 sync /* Wait for all dcbst to complete on bus */
929 7: sync /* Wait for all icbi to complete on bus */
933 * Re-point the IVPR at RAM
938 * We are done. Do not return, instead branch to second part of board
939 * initialization, now running from RAM.
942 addi r0,r10,in_ram - _start + _START_OFFSET
944 blr /* NEVER RETURNS! */
949 * Relocation Function, r14 point to got2+0x8000
951 * Adjust got2 pointers, no need to check for 0, this code
952 * already puts a few entries in the table.
954 li r0,__got2_entries@sectoff@l
955 la r3,GOT(_GOT2_TABLE_)
956 lwz r11,GOT(_GOT2_TABLE_)
966 * Now adjust the fixups and the pointers to the fixups
967 * in case we need to move ourselves again.
969 2: li r0,__fixup_entries@sectoff@l
970 lwz r3,GOT(_FIXUP_TABLE_)
984 * Now clear BSS segment
986 lwz r3,GOT(__bss_start)
1000 mr r3,r9 /* Init Data pointer */
1001 mr r4,r10 /* Destination Address */
1005 * Copy exception vector code to low memory
1008 * r7: source address, r8: end address, r9: target address
1012 lwz r7,GOT(_start_of_vectors)
1013 lwz r8,GOT(_end_of_vectors)
1015 li r9,0x100 /* reset vector always at 0x100 */
1018 bgelr /* return if r7>=r8 - just in case */
1020 mflr r4 /* save link register */
1030 * relocate `hdlr' and `int_return' entries
1032 li r7,.L_CriticalInput - _start + _START_OFFSET
1034 li r7,.L_MachineCheck - _start + _START_OFFSET
1036 li r7,.L_DataStorage - _start + _START_OFFSET
1038 li r7,.L_InstStorage - _start + _START_OFFSET
1040 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1042 li r7,.L_Alignment - _start + _START_OFFSET
1044 li r7,.L_ProgramCheck - _start + _START_OFFSET
1046 li r7,.L_FPUnavailable - _start + _START_OFFSET
1048 li r7,.L_Decrementer - _start + _START_OFFSET
1050 li r7,.L_IntervalTimer - _start + _START_OFFSET
1051 li r8,_end_of_vectors - _start + _START_OFFSET
1054 addi r7,r7,0x100 /* next exception vector */
1061 mtlr r4 /* restore link register */
1065 * Function: relocate entries for one exception vector
1068 lwz r0,0(r7) /* hdlr ... */
1069 add r0,r0,r3 /* ... += dest_addr */
1072 lwz r0,4(r7) /* int_return ... */
1073 add r0,r0,r3 /* ... += dest_addr */
1078 .globl unlock_ram_in_cache
1079 unlock_ram_in_cache:
1080 /* invalidate the INIT_RAM section */
1081 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1082 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1085 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1088 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1092 /* Invalidate the TLB entries for the cache */
1093 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1094 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1107 mfspr r3,SPRN_L1CFG0
1109 rlwinm r5,r3,9,3 /* Extract cache block size */
1110 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1111 * are currently defined.
1114 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1115 * log2(number of ways)
1117 slw r5,r4,r5 /* r5 = cache block size */
1119 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1120 mulli r7,r7,13 /* An 8-way cache will require 13
1125 /* save off HID0 and set DCFA */
1127 ori r9,r8,HID0_DCFA@l
1134 1: lwz r3,0(r4) /* Load... */
1142 1: dcbf 0,r4 /* ...and flush. */
1155 #include "fixed_ivor.S"